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| m68hc08 microcontrollers freescale.com mc68hc908rk2 data sheet mc68hc908rk2 rev. 5.1 08/2005
mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc908rk2 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) october, 2003 5.0 reformatted to new publications standards n/a section 13. electrical specificatio ns ? updated with new information. 163 august, 2005 5.1 updated to meet freescale identity guidelines. throughout revision history mc68hc908rk2 data sheet, rev. 5.1 4 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 3 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 4 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 5 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 6 internal clock generator modu le (icg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 7 keyboard/external in terrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 8 low-voltage inhibit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 chapter 9 input/output (i/o) port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 10 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 chapter 11 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 12 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 chapter 13 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 chapter 14 order informatio n and mechanical s pecifications . . . . . . . . . . . . . . . . . . . . . 155 list of chapters mc68hc908rk2 data sheet, rev. 5.1 6 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.3 external reset (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.5 port a input/output pins (pta7, pta6/kbd6?pta1/kbd1, and pta0) . . . . . . . . . . . . . . . 19 1.4.6 port b input/output pins (ptb5, ptb4/tch1, ptb3/tclk, ptb2/tch0, ptb1, and ptb0/mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 input/output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 flash 2ts memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5.1 flash 2ts control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5.2 flash 2ts charge pump frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.3 flash 2ts erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2.5.4 flash 2ts program/margin read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.5 flash 2ts block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.6 flash 2ts block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.5.7 embedded program/erase routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5.8 embedded function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.8.1 rdvrrng routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.8.2 prgrnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5.8.3 erarnge routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.8.4 redprog routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.8.5 example routine calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.5.9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents mc68hc908rk2 data sheet, rev. 5.1 8 freescale semiconductor chapter 3 configuration register (config) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 4 computer operating properly module (cop) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.7 copd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.8 coprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.8 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 chapter 5 central processor unit (cpu) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 9 chapter 6 internal clock g enerator module (icg) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.1 clock enable circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.2 internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2.2 modulo n divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.2.3 frequency comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.2.4 digital loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.3 external clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3.1 external oscillator amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3.2 external clock input path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4 clock monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4.1 clock monitor reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4.2 internal clock activity detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.4.3 external clock activity detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.5 clock selection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.5.1 clock selection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.5.2 clock switching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4 usage notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4.1 switching clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4.2 enabling the clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.3 clock monitor interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.4 quantization error in dco output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.4.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.4.2 binary weighted divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4.3 variable-delay ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4.4 ring oscillator fine-adjust circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.5 switching internal clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.6 nominal frequency settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.6.1 settling to within 15% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.6.2 settling to within 5% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.6.3 total settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.7 improving settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.8 trimming frequency on the internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.6 configuration register option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.6.1 extslow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.7.1 icg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.7.2 icg multiplier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.3 icg trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.4 icg dco divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.7.5 icg dco stage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table of contents mc68hc908rk2 data sheet, rev. 5.1 10 freescale semiconductor chapter 7 keyboard/external inte rrupt module (kbi) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3.1 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3.2 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.3 kbi module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.4 keyboard interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.5 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.5 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.1 irq and keyboard status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 chapter 8 low-voltage inhibit (lvi) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.3.1 false trip protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3.2 short stop recovery option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 9 input/output (i/o) ports 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 chapter 10 system integrati on module (sim) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 11 10.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 08 10.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 10.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 chapter 11 timer interface module (tim) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.4.4 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 11.4.5 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.4.6 pulse-width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.4.7 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.4.8 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.4.9 pwm initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.5.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.5.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.5.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.6 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table of contents mc68hc908rk2 data sheet, rev. 5.1 12 freescale semiconductor 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.7.1 tim clock pin (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.7.2 tim channel i/o pins (tch0 and tch1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 11.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.8.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0 11.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 chapter 12 development support 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.2.1.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 36 12.2.1.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.1.4 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 37 12.2.2 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.3 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.3.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2.3.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.3 monitor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.3.1.1 monitor mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3.1.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3.1.3 echoing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3.1.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3.1.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 chapter 13 electrical specifications 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.5 1.8-volt to 3.3-volt dc electrical c haracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.6 3.0-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.7 2.0-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.8 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.9 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.10 lvi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 13 chapter 14 order information and mechanical specifications 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.3 20-pin plastic ssop package (case no. 940c-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.4 20-pin soic plastic package (case no. 751d-05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table of contents mc68hc908rk2 data sheet, rev. 5.1 14 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 15 chapter 1 general description 1.1 introduction the mc68hc908rk2 mcu is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). optimized for low- power operation and available in a small 20-pin ssop/soic package, this mcu is well suited for remote keyless entry (rke) transmitter designs. all mcus in the family use the enhanced m68hc08 central processor uni t (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 features features include: high-performance m68hc08 architecture fully upward-compatible object code wi th m6805, m146805, and m68hc05 families maximum internal bus frequency of 4 mhz at 3.3 volts maximum internal bus frequency of 2 mhz at 1.8 volts internal oscillator requiring no external components ? software selectable bus frequencies ? 25 percent accuracy with trim capability to 2 percent ? option to allow use of external clock sour ce or external crystal/ceramic resonator 2 kbytes of on-chip flash memory flash program memory security (1) 128 bytes of on-chip ram 16-bit, 2-channel timer interface module (tim) 14 general-purpose input/output (i/o) ports: ? six shared with keyboard wakeup function ? three shared with the timer module ? port a pins have 3-ma sink capabilities low-voltage inhibit module: ? 1.85-v detection forces mcu into reset ? 2.0-v detection sets indicator flag 6-bit keyboard interrupt with wakeup feature external asynchronous interrupt pin with internal pullup (irq ) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. general description mc68hc908rk2 data sheet, rev. 5.1 16 freescale semiconductor system protection features: ? computer operating properly (cop) reset ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset the mc68hc908rk2 is available in these packages: ? 20-pin plastic shrink small outline package (ssop) ? 20-pin small outline integrated circuit (soic) package low-power design with stop and wait modes master reset pin and power-on reset (por) ?40 to 85 celsius operation features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908rk2 mcu. mcu block diagram mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 17 figure 1-1. mc68hc908rk2 block diagram system integration module computer operating properly module security module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 32 bytes user flash ? 2031 bytes user ram ? 128 bytes monitor rom ? 768 bytes user flash vector space ? 14 bytes keyboard/interrupt module power internal bus ptb ddrb power-on reset module low-voltage inhibit module 2-channel timer module pta ddra software selectable internal oscillator module ptb5 ptb4/tch1 ptb3/tclk ptb2/tch0 ptb1 ptb0/mclk pta7 (2) pta6/kbd6 (2) (3) pta5/kbd5 (2) (3) pta4/kbd4 (2) (3) pta3/kbd3 (2) (3) pta2/kbd2 (2) (3) pta1/kbd1 (2) (3) pta0 (2) osc2 osc1 rst (1) irq (1) v dd v ss 1. pin contains integrated pullup resistor 2. high current sink pin 3. pin contains software selectable pullup resistor general description mc68hc908rk2 data sheet, rev. 5.1 18 freescale semiconductor 1.4 pin assignments figure 1-2 shows the pin assignments. figure 1-2. ssop/soic pin assignments 1.4.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to prov ide power supply bypassing at the mcu as shown in figure 1-3 . place the bypass capacitors as close to the mcu power pins as possible. use high-frequency-response ce ramic capacitors for c bypass . c bulk are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels. figure 1-3. power supply bypassing 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections to an external clock source or crystal/ceramic resonator. pta0 ptb0/mclk ptb1 ptb2/tch0 ptb4/tch1 ptb5 ptb3/tclk osc1 osc2 v ss pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 pta5/kbd5 pta6/kbd6 pta7 rst irq v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 mcu v dd c bulk v ss v dd + note: component values shown r epresent typical applications. c bypass 0.1 f pin assignments mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 19 1.4.3 external reset (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. the rst pin contains an internal pullup resistor. for additional information, see chapter 10 system integration module (sim) . 1.4.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. the irq pin contains an internal pullup resistor. 1.4.5 port a input/output pins (p ta7, pta6/kbd6?pta 1/kbd1, and pta0) port a is an 8-bit special function port that shares its pins with the keyboard interrupt. six port a pins (pta6?pta1) can be programmed to serv e as an external interrupt. once enabled, that pin will contain an internal pullup resistor. all port a pins are high-current sink pins. 1.4.6 port b input/output pins (p tb5, ptb4/tch1, ptb3/tclk, ptb2/tch0, ptb1, and ptb0/mclk) port b is a 6-bit, general-purpose, bidirectional i/o por t, with some of its pins shared with the timer (tim) module. general description mc68hc908rk2 data sheet, rev. 5.1 20 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 21 chapter 2 memory 2.1 introduction the memory map, shown in figure 2-1 , includes: 2031 bytes of user flash memory 128 bytes of random-access memory (ram) 14 bytes of user-defined vectors in flash memory 768 bytes of monitor read-only memory (rom) these definitions apply to the memory map repr esentation of reserved and unimplemented locations: reserved ? accessing a reserved location can have unpredictable effects on mcu operation. unimplemented ? accessing an unimplemented lo cation causes an illegal address reset. 2.2 input/output section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00 ? sim break status register, sbsr $fe01 ? sim reset status register, srsr $fe02 ? sim break flag control register, bfcr $fe08 ? flash control register, flcr $fe0c ? break address register high, brkh $fe0d ? break address register low, brkl $fe0e ? break status and control register, bscr $fe0f ? lvi status register, lvisr $fff0 ? flash block protection register, flbpr $ffff ? cop control register, copctl memory mc68hc908rk2 data sheet, rev. 5.1 22 freescale semiconductor $0000 $003f i/o registers 28 bytes $0040 $007f unimplemented 64 bytes $0080 $00ff ram 128 bytes $0100 $77ff unimplemented 30,464 bytes $7800 $7fee flash memory 2031 bytes $7fef optional factory determined icg trim value (1) $7ff0 $efff unimplemented 28,688 bytes $f000 $f2ef monitor rom 752 bytes $f2f0 $fdff unimplemented 2832 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 sim break flag control register (sbfcr) $fe03 $fe06 reserved 4 bytes $fe07 unimplemented $fe08 flash control register (flcr) $fe09 reserved $fe0a $fe0b unimplemented 2 bytes $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (bscr) $fe0f lvi status register (lvisr) $fe10 $feef unimplemented 222 bytes continued on next page figure 2-1. memory map input/output section mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 23 $fef0 $feff monitor rom 16 bytes $ff00 $ffef unimplemented 240 bytes $fff0 flash block protect register (flbpr) $fff1 reserved $fff2 $ffff flash vectors 14 bytes 1. address $7fef is reserved for an optional factory-determined icg trim value. consult with a local freescale representative for more information and availability of this option. addr. register name bit 7654321bit 0 $0000 port a data register (pta) see page 98. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 100. read: ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 $0003 unimplemented $0004 data direction register a (ddra) see page 98. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 100. read: mclken 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 $0019 unimplemented = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 1 of 5) figure 2-1. memory map (continued) memory mc68hc908rk2 data sheet, rev. 5.1 24 freescale semiconductor $001a irq and keyboard status and control register (intkbscr) see page 90. read: irqf 0 imaski modei keyf 0 imaskk modek write: r acki r ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 91. read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 0 write: reset:00000000 $001c $001e unimplemented $001f configuration register (config) see page 41. read: extslow lvistop lvirst lvipwr coprs ssrec stop copd write: reset:00110000 $0020 timer status and control register (tsc) see page 128. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (tcnth) see page 129. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer counter register low (tcntl) see page 129. read:bit 7654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (tmodh) see page 130. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer counter modulo register low (tmodl) see page 130. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (tsc0) see page 131. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (tch0h) see page 134. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 2 of 5) input/output section mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 25 $0027 timer channel 0 register low (tch0l) see page 134. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (tsc1) see page 131. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer channel 1 register high (tch1h)) see page 134. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (tch1l)) see page 134. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b $0035 unimplemented $0036 internal clock generator control register (icgcr) see page 79. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: reset:00001000 $0037 internal clock generator multiplier register (icgmr) see page 81. read: r n6n5n4n3n2n1n0 write: reset:00010101 $0038 internal clock generator trim register (icgtr) see page 81. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 icg dco divider control register (icgdvr) see page 82. read: rrrrddiv3ddiv2ddiv1ddiv0 write: reset:0000 uuuu $003a icg dco stage register (icgdsr) see page 82. read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write: reset: unaffected by reset $003b reserved rrrrrrrr addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 3 of 5) memory mc68hc908rk2 data sheet, rev. 5.1 26 freescale semiconductor $003c $003f unimplemented $fe00 sim break status register (sbsr) see page 115. read: rrrrrr sbsw r write: see note reset: 0 note: writing a 0 clears sbsw $fe01 sim reset status register (srsr) see page 116. read: por pin cop ilop ilad 0 lvi 0 write: por:1xxxxxxx $fe02 sim break flag control register (sbfcr) see page 117. read: bcferrrrrrr write: reset:00000000 $fe03 $fe04 reserved rrrrrrrr $fe05 $fe07 unimplemented $fe08 flash 2ts control register (flcr) see page 30. read: 0 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 $fe09 reserved rrrrrrrr $fe0a $fe0b unimplemented $fe0c break address register high (brkh) see page 138. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 4 of 5) input/output section mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 27 $fe0d break address register low (brkl) see page 138. read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (bscr) see page 137. read: brke brka 000000 write: reset:00000000 $fe0f lvi status register (lvisr) see page 94. read:lviout0lowv00000 write: reset:00000000 $fff0 flash 2ts block protect register (flbpr) ? see page 34. read: rrrrbpr3bpr2bpr1bpr0 write: reset: unaffected by reset ? non-volatile flash register $ffff cop control register (copctl) see page 45. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and data registers (sheet 5 of 5) memory mc68hc908rk2 data sheet, rev. 5.1 28 freescale semiconductor table 2-1 is a list of vector locations. 2.3 monitor rom the 768 bytes at addresses $f000?f2ef and $fef0?$feff are utilized by the monitor rom. the address range $f000?f2ef is reserved for the monitor code functions, flash memory programming, and erase algorithms. the address range $fef0?$feff holds reserved rom addresses that contain the monitor code reset vectors. 2.4 random-access memory (ram) addresses $0080?$00ff are ram locations. the location of the stack ram is programmable. note for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m68hc05, m6805, and m146805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or dur ing the interrupt stacking operation. table 2-1. vector locations address vector low $fff2 icg vector (high) $fff3 icg vector (low) priority $fff4 tim overflow vector (high) $fff5 tim overflow vector (low) $fff6 tim channel 1 vector (high) $fff7 tim channel 1 vector (low) $fff8 tim channel 0 vector (high) $fff9 tim channel 0 vector (low) $fffa irq/keyboard vector (high) $fffb irq/keyboard vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 29 2.5 flash 2ts memory this subsection describes the o peration of the embedded flash 2ts memory. this memory can be read, programmed, and erased from a single extern al supply. the program and erase operations are enabled through the use of an internal charge pump. the flash 2ts memory is appropriately named to describe its two-transistor source-select bit cell. the flash 2ts memory is an array of 2031 bytes with an additional 14 bytes of us er vectors and one byte for block protection. an erased bit reads as a 0 and a programmed bit reads as a 1. the address ranges for the user memory, control register, and vectors are: $7800?$7fee, user space $7fef, reserved ? optional icg trim value, see 6.7.3 icg trim register $fff0, block protect register $fe08, flash 2ts control register $fff2?$ffff, these locations are reserved for user-defined interrupt and reset vectors this list is the row architecture for the user space array: $7800?$7807 (row 0) $7808?$780f (row 1) $7810?$7817 (row 2) $7818?$781f (row 3) $7820?$7827 (row 4) -------------------------- $7fe8?$7fef (row 253) program and erase operations are facilitated through c ontrol bits in a memory mapped register. details for these operations appear later in this section. memory in the flash 2ts array is organized into pages within rows. for the 2-kbyte array on the mc68hc908rk2, the page size is one byte. there are eight pages (or eight bytes) per row. programming opera tions are performed on a page basis, one byte at time. erase operations are performed on a block basis. the mini mum block size is one row of eight bytes. refer to table 2-3 for additional block size options. note sometimes a program disturb condition, in which case an erased bit on the row being programmed unintentionally becomes programmed, occurs. the embedded smart programming algorithm implements a margin read technique to avoid program disturb. the margin read step of the smart programming algorithm is used to ensure programmed bits are programmed to sufficient margin for data retention over the device?s lifetime. in the application code, perform an erase operation after eight program operations (on the same row) to further avoid program disturb. for availability of programming tools and more info rmation, contact a local freescale representative. note a security feature prevents viewing of the flash 2ts contents. (1) 1. no security feature is abso lutely secure. however, freescale?s strategy is to make reading or copying the flash 2ts difficult for unauthorized users. memory mc68hc908rk2 data sheet, rev. 5.1 30 freescale semiconductor 2.5.1 flash 2ts control register the flash 2ts control register (flcr) controls program, erase, and margin read operations. fdiv0 ? frequency divide control bit this read/write bit selects the factor by which the c harge pump clock is divided from the system clock. see 2.5.2 flash 2ts charge pump frequency control . blk1 ? block erase control bit this read/write bit together with blk0 allows erasing of blocks of varying size. see 2.5.3 flash 2ts erase operation for a description of available block sizes. blk0 ? block erase control bit this read/write bit together with blk1 allows erasing of blocks of varying size. see 2.5.3 flash 2ts erase operation for a description of available block sizes. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can be set only if either pg m = 1 or erase = 1 and the proper sequence for smart programming or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off margin ? margin read control bit this read/write bit configures the memory for ma rgin read operation. margin cannot be set if the hven = 1. margin will automatically return to unset (0) if asserted when hven = 1. 1 = margin read operation selected 0 = margin read operation unselected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be set at the same time. 1 = program operation selected 0 = program operation unselected address: $fe08 bit 7654321bit 0 read: 0 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 = unimplemented figure 2-3. flash 2ts control register (flcr) flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 31 2.5.2 flash 2ts char ge pump frequency control the internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2-mhz clock. the charge pump clock is derived from the bus clock. table 2-2 shows how the fdiv bits are used to select a charge pump frequency based on the bus clock frequency. program, margin read, and erase operations cannot be performed if the bus clock frequency is below 2 mhz. note the charge pump is optimized for 2-mhz operation. 2.5.3 flash 2t s erase operation use this step-by-step procedure to erase a block of flash 2ts memory. refer to 13.11 memory characteristics for a detailed description of the times used in this algorithm. 1. set the erase, blk0, blk1, and fdiv0 bits in the flash 2ts control register. refer to table 2-2 for fdiv settings and to table 2-3 for block sizes. 2. ensure target portion of array is unprotected by reading the block protect register at address $fff0. refer to 2.5.5 flash 2ts block protection and 2.5.6 flash 2ts block protect register for more information. 3. write to any flash 2ts address with any data within the block address range desired. 4. set the hven bit. 5. wait for a time, t erase . 6. clear the hven bit. 7. wait for a time, t kill , for the high voltages to dissipate. 8. clear the erase bit. 9. after a time, t hvd , the memory can be accessed in read mode again. note while these operations must be performed in the order shown, other unrelated operations may occur between the steps. table 2-3 shows the various block sizes which can be erased in one erase operation. in step 3 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. for instance, with blk0 = blk1 = 0, writing to any flash 2ts address in the range $7800 to $78f0 will enable the erase of all flash memory. table 2-2. charge pump clock frequency fdiv0 pump clock frequency 0 bus frequency 1 1 bus frequency 2 table 2-3. erase block sizes blk1 blk0 block size, addresses cared 0 0 full array: 2 kbytes 0 1 one-half array: 1 kbytes 1 0 eight rows: 64 bytes 1 1 single row: 8 bytes memory mc68hc908rk2 data sheet, rev. 5.1 32 freescale semiconductor 2.5.4 flash 2ts program /margin read operation note after a total of eight program operations have been applied to a row, the row must be erased before further programming to avoid program disturb. an erased byte will read $00. the flash 2ts memory is programmed on a page bas is. a page consists of one byte. the smart programming algorithm ( figure 2-4 ) is recommended to program every page in the flash 2ts memory. the embedded smart programming algorithm uses this step-by-step sequence to program the data into the flash memory. the algorithm optimizes the time required to program each page. refer to 2.5.7 embedded program/erase routines for information on ut ilizing embedded routines. 1. set the fdiv bits. these bits determine the charge pump frequency. 2. set pgm = 1. this configures the memory fo r program operation and enables the latching of address and data for programming. 3. read the flash 2ts block protect register (flbpr). 4. write data to the one byte being programmed. 5. set hven = 1. 6. wait for a time, t step . 7. set hven = 0. 8. wait for a time, t hvtv . 9. set margin = 1. 10. wait for a time, t vtp . 11. set pgm = 0. 12. wait for a time, t hvd . 13. read back data in margin read mode. this read operation is stretched by eight cycles. 14. clear the margin bit. if the margin read data is identical to write data, the program operation is complete; otherwise, jump to step 2. note while these operations must be performed in the order shown, other unrelated operations may occur between the steps. the smart programming algorithm guarant ees the minimum possible program time. flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 33 figure 2-4. smart programming algorithm flowchart program flash 2ts initialize attempt counter set pgm bit and fdiv bits wait t hvtv wait t vtp set hven bit clear pgm bit set margin bit wait t hvd increment attempt counter y n to 0 y n programming operation failed programming operation complete write data to selected page wait t step clear hven bit margin read page of data clear margin bit margin read data equal to write data? read flash block protect reg. page program/margin read procedure note: this page program algorithm assumes the page/s to be programmed are initially erased. note: this algorithm is mandatory for programming the flash 2ts. set interrupt mask: clear margin bit clear interrupt mask: sei instruction cli instruction attempt count equal to fls pulses ? memory mc68hc908rk2 data sheet, rev. 5.1 34 freescale semiconductor 2.5.5 flash 2ts block protection note in performing a program or erase operation, the flash 2ts block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. due to the ability of the on-board charge pump to erase and program the flash 2ts memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is implemented by a reserved location in the memory for block protect information. this block prot ect register must be read before setting hven = 1. when the block protect register is read, its contents are latched by the flash 2ts control logic. if the address range for an erase or program operation in cludes a protected block, the pgm or erase bit is cleared which prevents the hven bit in the flash 2ts control register from being set such that no high-voltage operation is allowed in the array. when the block protect register is er ased (all 0s), the entire memory is accessible for program and erase. when bits within the register are programmed, they lo ck blocks of memory address ranges as shown in 2.5.6 flash 2ts block protect register . the block protect register itself can be erased or programmed only with an external voltage v tst present on the irq pin. the presence of v tst on the irq pin also allows entry into monitor mode out of reset. therefore, the ability to change the block protect register is voltage-level dependent and can occur in either user or monitor modes. 2.5.6 flash 2ts blo ck protect register the block protect register (flbpr) is implemented as a byte within the flash 2ts memory. each bit, when programmed, protects a range of addresses in the flash 2ts. bpr3 ? block protect register bit 3 this bit protects the memory contents in the address ranges $7a00?$7fef and $fff0?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr2 ? block protect register bit 2 this bit protects the memory contents in the address ranges $7900?$7fef and $fff0?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr1 ? block protect register bit 1 this bit protects the memory contents in the address ranges $7880?$7fef and $fff0?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program address: $fff0 bit 7654321bit 0 read: rrrrbpr3bpr2bpr1bpr0 write: reset: unaffected by reset r= reserved figure 2-5. flash 2ts block protect register (flbpr) flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 35 bpr0 ? block protect register bit 0 this bit protects the flash memory contents in the address ranges $7800?$7fef and $fff0?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program by programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. programming more than one bit at a time is redundant. if both bit 1 and bit 2 are set, for instance, the flash address ranges between $7880?$ffff are locked. if all bits are erased, then all of the memo ry is available for erase and program. the presence of a voltage v tst on the irq pin will bypass the block prot ection so that all of memory, including the block protect register, can be programmed or erased. 2.5.7 embedded program/erase routines the mc68hc908rk2 monitor rom contains numero us routines for programming and erasing the flash memory. these embedded routines are intended to assist the programmer with modifying the flash memory array. these routines will implem ent the smart programming algorithm as defined in figure 2-4 . the functions are listed in table 2-4 . the functions shown in table 2-4 accept data through the cpu registers and global variables in ram. table 2-5 shows the ram locations that are used for passing parameters. table 2-4. embedded flash routines function description call jsr to address (1) 1. romstrt is defined as the starti ng address of the monitor rom in the memory map. this is address $f000. read/verify a range rdvrrng romstrt + 0 program range of flash prgrnge romstrt + 3 erase range of flash erarnge romstrt + 6 redundant program flash redprog romstrt + 9 table 2-5. embedded flash routine global variables variable location variable address (1) 1. ramstart is defined as the starting address of the ram in the memory map. this is address $0080. ctrlbyt ramstart + 8 cpuspd ramstart + 9 laddr ramstart + 10 bumps ramstart + 12 derase ramstart + 13 data ramstart + 15 memory mc68hc908rk2 data sheet, rev. 5.1 36 freescale semiconductor 2.5.8 embedded func tion descriptions this subsection describes the embedded functions. 2.5.8.1 rdvrrng routine name: rdvrrng purpose: read and/or verify a range of flash memory entry conditions: h:x contains t he first address of the range laddr contains the last address of the range data contains the data to compare the read data against for read/verify to ram only (length is user determined) acc non-zero for read/verify to ram, 0 for output to pa0 exit conditions: c bit set if good compare for read/verify to ram only acc contains checksum data contains read flash data for read/verify to ram only ready/verify ram option: this subroutine both compares data passed in the data array to the flash data and reads the data from flash into the data array. it also calculates the checksum of the data. output to pa0 option: this subroutine dumps the data from the range to pa0 in the same format as monitor data. it also calculat es the checksum of the data. note this serial dump does not circumvent security because the security vectors must still be passed to make flash readable in monitor mode. 2.5.8.2 prgrnge routine name: prgrnge purpose: programs a range of addresses in flash memory entry conditions: h:x contains t he first address in the range laddr contains the last address in the range data contains the data to be programmed (length is user determined) cpuspd contains the bus frequency times 4 in mhz bumps contains the maximum al lowable number of programming bumps to use exit conditions: c bit set if successful program; cleared otherwise i bit set, masking interrupts this routine programs a range of flash defined by h:x and laddr. the range can be from one byte to as much ram as can be allocated to data . the smart programming algorithm defined in 2.5.4 flash 2ts program/margin read operation is used. flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 37 2.5.8.3 erarnge routine name: erarnge purpose: erase a range of addresses in flash memory entry conditions: h:x contains an address in the range to be erased; range size specified by control byte ctlbyte contains the erase block size in bits 5 and 6 (see table 2-6 ) derase contains the erase delay time in s/24 cpuspd cpu frequency times 4 in mhz exit conditions: i bit set, masking interrupts. this routine erases the block of flash defined by h:x and ctlbyte. the algorithm defined in 2.5.3 flash 2ts erase operation is used. preserves the contents of h:x (address passed) 2.5.8.4 redprog routine name: redprog purpose: this routine will use a range of mu ltiple rows in the flash array to emulate increased write/erase cycli ng capability of one row. entry conditions: h:x contains the address of the first row in the range. this address must be the first address of a row (multiple of eight bytes) laddr address of last row in the range; must be the first address of a row (multiple of eight bytes) data data to program in the row (bit 7 of data + 0 is used internally and will be overwritten). routine will always use 8 bytes starting at data bumps contains the maximum al lowable number of programming bumps to use cpuspd contains the bus frequency times 4 in mhz derase contains the erase delay time in s/24 exit conditions: c bit set if successful program; cleared otherwise i bit set, masking interrupts this routine uses a range of the flash array containi ng multiple rows to emulate increased write/erase cycling capability for data storage. t he routine will write data to each row of the flash array (in the range table 2-6. ctlbyte-erase block size bit 6 bit 5 block size 0 0 full array 0 1 one half array 1 0 eight rows: 64 pages 1 1 single row: 8 pages memory mc68hc908rk2 data sheet, rev. 5.1 38 freescale semiconductor defined) upon subsequent calls. the number of rows is the difference between the value in h:x and laddr, divided by 8. a row is the minimum range that can be programmed with the redprog routine. all rows in the range will be programmed once before any are programmed agai n. this approach is taken to ensure that all rows reach the end of lifetime at approximately the same time. a special bit will be maintained by the routine, called a cycling bit, in each row. this bit is used to ensure that the data is programmed to all t he rows defined in the range. this is the high bit of the first byte in each row. this bit cannot be used to store user data. it will be modified by the redprog routine. this is at bit 7 of the byte at address data+0. to determine which row to program, the algorithm will st ep from the first to the last row in a range looking for the first row whose cycling bit is different from the first. if all ro ws contain the same cycling bit, then the first row will be used. the row whose cycling bit is different will be erased and the entire row will be programmed with the given data, including a toggled version of the cycling bit. 2.5.8.5 example routine calls this code is for illustrative purposes only and does not represent valid syntax for any particular assembler. ram equ $80 rdvrrng equ $f000 prgrnge equ $f003 eranrge equ $f006 redprog equ $f009 ;************************************************************* ram definitions for subroutines ;************************************************************** org ram+8 ctrlbyt rmb 1 cpuspd rmb 1 laddr rmb 2 bumps rmb 1 derase rmb 2 ;allocation of ?data? space is dependent on the device and ;application data rmb 8 ;************************************************************* ; calling example for read/verify a range (rdvrrng) ;************************************************************** lda #$ff ;target is ram ldhx #$7807 ;end after first row sthx laddr ldhx #$7800 ;start at first row jsr rdvrrng ;data will contain flash info flash 2ts memory mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 39 ;*************************************************************; calling example for erase a range (rngeera) ;************************************************************** mov #$08,cpuspd ;load bus frequency in mhz * 4 mov #$60,ctrlbyt ;bits 5&6 hold the block size to erase ;00 full array ;20 one-half array ;40 eight rows ;60 singe row ;remember a row is 1 byte ;set erase time in us/24, number in ;decimal ldhx #100000/24 sthx derase ldhx #$7800 ;address in the range to erase jsr erarnge ;call through jump table ;************************************************************; ; calling example for program a range (rngeprog) ;************************************************************* mov #?p?,data mov #?r?,data+1 mov #?o?,data+2 mov #?g?,data+3 mov #?t?,data+4 mov #?e?,data+5 mov #?s?,data+6 mov #?t?,data+7 mov #$08,cpuspd ;load bus frequency in mhz * 4 mov #$0a,bumps ;load max number of programming steps ;before a failure is returned ldhx #$7807 ;load the last address to program sthx laddr ;into laddr ldhx #$7800 ;load the first address to program ;into h:x ;this range may cross page boundaries ;and may be any length, so long as the ;data to program is loaded in ram ;beginning at data. jsr prgrnge ;call through jump table. ;************************************************************** ; calling example for redundant program a row (redprog) ;************************************************************** mov #$56,data mov #?p?,data+1 mov #?r?,data+2 mov #?o?,data+3 mov #?g?,data+4 mov #?r?,data+5 mov #?e?,data+6 mov #?d?,data+7 memory mc68hc908rk2 data sheet, rev. 5.1 40 freescale semiconductor mov #$08,cpuspd ;load bus frequency in mhz * 4 mov #$0a,bumps ;load max number of programming steps ;before a failure is returned ;set erase time in us/24 ldhx #100000/24 sthx derase ldhx #$7808 ;load the last address of the multi-row ;range; (in this case, 2 rows) sthx laddr ;into laddr ldhx #$7800 ;load the first address of the ;multi-row range into h:x jsr redprog ;call through jump table. 2.5.9 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 2.5.9.1 wait mode putting the mcu into wait mode while the flash 2ts is in read mode does not affect the operation of the flash 2ts memory directly, but there will be no memory activity sinc e the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash 2ts. when the mcu is put into wait mode, the charge pump for the flash 2ts is disabled so that either a program or erase operation will not continue. if the memory is in either program mode (pgm = 1, hven = 1) or erase mode (erase = 1, hven= 1), then it will remain in that mode during wait. exit from wait mode must now be done with a reset ra ther than an interrupt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. 2.5.9.2 stop mode when the mcu is put into stop mode, if the flash 2ts is in read mode, it will be put into low-power standby. the stop instruction should not be executed while performing a program or erase operation on the flash 2ts. when the mcu is put into stop mode, the charge pump for the flash 2ts is disabled so that either a program or erase operation will not continue. if the memory is in either program mode (pgm = 1, hven = 1) or erase mode (erase = 1, hven = 1), then it will remain in that mode during stop. exit from stop mode now must be done with a reset rat her than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 41 chapter 3 configuration register (config) 3.1 introduction this section describes the configuration register (config). the configuration register enables or disables these options: stop mode recovery time (32 cgmxcl k cycles or 4,096 cgmxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 cgmxclk cycles) stop instruction computer operating properly module (cop) low-voltage inhibit (lvi) module control 3.2 functional description the config register is used in the initialization of various options and can be written once after each reset. the register is set to the documented val ue during reset. since the various options affect the operation of the mcu, it is recommended that these registers be written immediately after reset. the configuration register is located at $001f. note on a flash device, the options are one-time writable by the user after each reset. the config register is not in the flash memory but is a special register containing one-time writable latches after each reset. upon a reset, the config register defaults to predetermined settings as shown in figure 2-1. memory map . extslow ? slow external crystal enable bit the extslow bit has two functions. it configures the icg module for a fast (1 mhz?8 mhz) or slow (30 khz?100 khz) speed crystal. the option also configures the clock monitor operation in the icg module to expect an external frequency higher (307. 2 khz?32 mhz) or lower (60 hz?307.2 khz) than the base frequency of the internal oscillator. see chapter 6 internal clock generator module (icg) . 1 = icg set for slow external crystal operation 0 = icg set for fast external crystal operation address: $001f bit 7654321bit 0 read: extslow lvistop lvirst lvipwr coprs ssrec stop copd write: reset:0 0110000 figure 3-1. configuration register (config) configuration register (config) mc68hc908rk2 data sheet, rev. 5.1 42 freescale semiconductor lvistop ? lvi enable in stop mode bit when the lvipwr bit is set, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirst ? lvi reset enable bit lvirst enables the reset signal from the lvi module. see chapter 8 low-voltage inhibit (lvi) . 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr disables the lvi module. see chapter 8 low-voltage inhibit (lvi) . 1 = lvi module power enabled 0 = lvi module power disabled coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. see chapter 4 computer operating properly module (cop) . 1 = cop timeout period = 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 ? 2 4 cgmxclk cycles ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note exiting stop mode by pulling reset will result in the long stop recovery. if using the internal clock generator modu le or an external crystal oscillator, do not set the ssrec bit. the lvi has an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 cgmxclk cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not pr otected from a low power condition. however, when using the short stop recovery configuration option, the 32 cgmxclk delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 4 computer operating properly module (cop) . 1 = cop module disabled 0 = cop module enabled mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 43 chapter 4 computer operating properly module (cop) 4.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter. 4.2 functional description figure 4-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 13 ?2 4 or 2 18 ?2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the configuration register. when coprs = 1, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location copctl write cgmxclk reset vector fetch reset reset status internal reset sources stop instruction clear stages 5?12 clear all stages 6-bit cop counter copd from config reset copctl write clear cop counter coprs from config 12-bit cop prescaler register computer operating properly module (cop) mc68hc908rk2 data sheet, rev. 5.1 44 freescale semiconductor $ffff before an overflow occurs prevents a cop re set by clearing the cop counter and stages 5 through 12 of the prescaler. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq pin is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 4.3 i/o signals the following paragraphs describe the signals shown in figure 4-1 . 4.3.1 cgmxclk cgmxclk is the oscillator output signal. see 6.3.5 clock selection circuit for a description of cgmxclk. 4.3.2 stop instruction the stop instruction clears the cop prescaler. 4.3.3 copctl write writing any value to the cop control register (copctl) (see 4.4 cop control register ), clears the cop counter and clears stages 12 through 5 of the cop prescaler. reading the cop control register returns the reset vector. 4.3.4 powe r-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power up. 4.3.5 internal reset an internal reset clears the cop prescaler and the cop counter. 4.3.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 4.3.7 copd the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. see chapter 3 configuration register (config) . cop control register mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 45 4.3.8 coprs the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register. see chapter 3 configuration register (config) . 4.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 4.5 interrupts the cop does not generate cpu interrupt requests. 4.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin or on the rst pin. 4.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 4.7.1 wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 4.7.2 stop mode stop mode turns off the cgmxclk input to the co p and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit (see chapter 3 configuration register (config) ) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 4.8 cop module during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 4-2. cop control register (copctl) computer operating properly module (cop) mc68hc908rk2 data sheet, rev. 5.1 46 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 47 chapter 5 central processor unit (cpu) 5.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 5.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 5.3 cpu registers figure 5-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc908rk2 data sheet, rev. 5.1 48 freescale semiconductor figure 5-1. cpu registers 5.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 5.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 5-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 5-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 49 5.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 5.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 5-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 5-5. program counter (pc) central processor unit (cpu) mc68hc908rk2 data sheet, rev. 5.1 50 freescale semiconductor 5.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 5-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 51 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 5.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 5.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 5.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 5.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 5.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) mc68hc908rk2 data sheet, rev. 5.1 52 freescale semiconductor 5.7 instruction set summary table 5-1 provides a summary of the m68hc08 instruction set. table 5-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c instruction set summary mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 53 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 5-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908rk2 data sheet, rev. 5.1 54 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 5-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc instruction set summary mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 55 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 5-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc908rk2 data sheet, rev. 5.1 56 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 5-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c opcode map mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 57 5.8 opcode map see table 5-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 5-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc908rk2 data sheet, rev. 5.1 58 freescale semiconductor central processor unit (cpu) table 5-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 59 chapter 6 internal clock generator module (icg) 6.1 introduction the internal clock generator (icg) is used to create a stable clock source for the microcontroller without using any external components. the icg generates t he oscillator output cloc k (cgmxclk), which is used by the cop, lvi, and other modules. the icg also generates the clock generator output (cgmout), which is fed to the system integrati on module (sim) to create the bus clocks. the bus frequency will be one-fourth the frequency of cgmxclk and one-half the frequency of cgmout. 6.2 features the icg has these features: external clock generator, either 1-pin external source or 2-pin crystal internal clock generator with programmable frequenc y output in integer multiples of a nominal frequency (307.2 khz 25%) frequency adjust (trim) regist er to improve variability to 2% bus clock software selectable from either internal or external clock clock monitor for both internal and external clocks 6.3 functional description the icg, shown in figure 6-2 , contains these major submodules: clock enable circuit internal clock generator external clock generator clock monitor circuit clock selection circuit 6.3.1 clock enable circuit the clock enable circuit is used to enable the internal clock (iclk) or external clock (eclk). the clock enable circuit generates an icg stop (icgstop) signal which stops all clocks (iclk, eclk, and the low-frequency base clock, ibase) low. icgsto p is set and the icg is disabled in stop mode. the internal clock enable signal (icgen) turns on th e internal clock generator which generates iclk. icgen is set (active) whenever the icgon bit is set and the icgstop signal is clear. when icgen is clear, iclk and ibase are both low. the external clock enable signal (ecgen) turns on the external clock generator which generates eclk. ecgen is set (active) whenever the ecgon bit is set and the icgstop signal is clear. when ecgen is clear, eclk is low. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 60 freescale semiconductor figure 6-1. block diagram highlighting icg block and pins system integration module computer operating properly module security module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 32 bytes user flash ? 2031 bytes user ram ? 128 bytes monitor rom ? 768 bytes user flash vector space ? 14 bytes keyboard/interrupt module power internal bus ptb ddrb power-on reset module low-voltage inhibit module 2-channel timer module pta ddra software selectable internal oscillator module ptb5 ptb4/tch1 ptb3/tclk ptb2/tch0 ptb1 ptb0/mclk pta7 (2) pta6/kbd6 (2) (3) pta5/kbd5 (2) (3) pta4/kbd4 (2) (3) pta3/kbd3 (2) (3) pta2/kbd2 (2) (3) pta1/kbd1 (2) (3) pta0 (2) osc2 osc1 rst (1) irq (1) v dd v ss 1. pin contains integrated pullup resistor 2. high current sink pin 3. pin contains software selectable pullup resistor functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 61 figure 6-2. icg module block diagram internal to mcu external external clock generator ecgs osc1 osc2 simoscen ibase icgs cmon cpu_int n[6:0] trim[7:0] clock monitor/switcher circuit cmf eclk iclk clock selection eoff ioff cgmxclk cs cgmout extslow clock enable circuit icgon ecgon ecgen icgen dstg reset ddiv name name name name configuration register bit top level signal register bit module signal circuit internal clock generator internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 62 freescale semiconductor 6.3.2 internal clock generator the internal clock generator, shown in figure 6-3 , creates a low-frequency base clock (ibase), which operates at a nominal frequency (f nom ) of 307.2 khz 25%, and an internal clock (iclk) which is an integer multiple of ibase. this multiple is the icg mu ltiplier factor (n), which is programmed in the icg multiplier register (icgmr). the internal clock generator is turned off and the output clocks (ibase and iclk) are held low when the internal clock generator enable signal (icgen) is clear. figure 6-3. internal clock generator block diagram the internal clock generator contains: a digitally controlled oscillator a modulo n divider a frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators a digital loop filter 6.3.2.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk). the clock period of iclk is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because there is only a li mited number of bits in ddiv and dstg, the precision of the output (iclk) is restricted to a long-term precision of approximately 0.202% to 0.368% when measured over several cycles (of the desired frequency). additionally, since the propagation delays of the devices used in the dco ring oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require alternately running faster and slower th an desired, making the worst case cycle-to-cycle frequency variation 6.45% to 11.8% (of the desired frequency). the valid values of ddiv:dstg range from $000 to $9ff. for more information on the quantization error in the dco, see 6.4.4 quantization error in dco output . digitally controlled oscillator iclk modulo n divider frequency comparator clock generator trim[7:0] voltage & current references digital loop filter ++ + ? ? ? n[6:0] dstg[7:0] icgen ibase ddiv[3:0] name name register bit module signal functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 63 6.3.2.2 modulo n divider the modulo n divider creates the lo w-frequency base clock (i base) by dividing the internal clock (iclk) by the icg multiplier factor (n) contained in the ic g multiplier register (icgmr). when n is programmed to a $01 or $00, the divider is di sabled and iclk is passed through to ibase undivided. when the internal clock generator is stable, the frequency of ibase will be equal to the nominal frequency (f nom ) of 307.2 khz 25%. 6.3.2.3 frequency comparator the frequency comparator effectiv ely compares the low-frequency base clock (ibase) to a nominal frequency, f nom . first, the frequency comparator converts ibase to a voltage by charging a known capacitor with a current reference for a period dependent on ibase. this voltage is compared to a voltage reference with comparators, whose outputs are fed to the digital loop filter. the dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to 25 percent error in f nom . 6.3.2.4 digital loop filter the digital loop filter (dlf) uses the outputs of the frequency comparator to adjust the internal clock (iclk) clock period. the dlf generates the dco divider control bits (ddiv[3:0]) and the dco stage control bits (dstg[7:0]), which are fed to t he dco. the dlf first concatenates the ddiv and dstg registers (ddiv[3:0]:dstg[7:0]) and then adds or subtracts a value dependent on the relative error in the low-frequency base clock?s period, as shown in table 6-1 . in some extreme error conditions, such as operating at a v dd level which is out of specification, the dlf may attempt to use a value above the maximum ($9ff) or below the minimum ($000). in both cases, the value for ddiv will be between $a and $f. in this range, the ddiv value will be interpret ed the same as $9 (the slowest condition). recovering from this condition requires subtracting (increasing frequency) in the normal fashion until the value is again below $9ff (if the desired value is $9xx, the va lue may settle at $axx through $fxx, an acceptable operating condition). if the error is less than 5%, the internal clock generator?s filter stable indicator (ficgs) is set, indicating relative fr equency accuracy to the clock monitor. table 6-1. correction sizes from dlf to dco frequency error of ibase compared to f nom ddvi[3:0]: dstg[7:0] correction current to new ddiv[3:0]:dstg[7:0] relative correction in dco ibase < 0.85 f nom ?32 (?$020) min $xff to $xdf ?2/31 ?6.45% max $x20 to $x00 ?2/19 ?10.5% 0.85 f nom < ibase ibase < 0.95 f nom ?8 (?$008) min $xff to $xf7 ?0.5/31 ?1.61% max $x08 to $x00 ?0.5/17.5 ?2.86% 0.95 f nom < ibase ibase < f nom ?1 (?$001) min $xff to $xfe ?0.0625/31 ?0.202% max $x01 to $x00 ?0.0625/17.0625 ?0.366% f nom < ibase ibase < 1.05 f nom +1 (+$001) min $xfe to $xff +0.0625/30.9375 +0.202% max $x00 to $x01 +0.0625/17 +0.368% 1.05 f nom < ibase ibase < 1.15 f nom +8 (+$008) min $xf7 to $xff +0.5/30.5 +1.64% max $x00 to $x08 +0.5/17 +2.94% 1.15 f nom < ibase +32 (+$020) min $xdf to $xff +2/29 +6.90% max $x00 to $x20 +2/17 +11.8% x: maximum error is independe nt of value in ddiv[3:0]. ddiv increments or decrements when an addition to dstg[7:0] carries or borrows. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 64 freescale semiconductor 6.3.3 external clock generator the icg also provides for an external oscillator or clock source, if desired. the external clock generator, shown in figure 6-4 , contains an external oscillator am plifier and an external clock input path. figure 6-4. external clock generator block diagram 6.3.3.1 external oscillator amplifier the external oscillator amplifier prov ides the gain required by an external crystal connected in a pierce oscillator configuration. the amount of this gain is controlled by the slow external (extslow) bit in the configuration register. when extslow is set, the amplifier gain is reduced for operating low-frequency crystals (32 khz to 100 khz). when extslow is clear , the amplifier gain will be sufficient for 1-mhz to 8-mhz crystals. extslow must be configured correctly for the given crystal or the circuit may not operate. the amplifier is enabled when the ecgon bit is set and stop mode is not enabled. when the amplifier is enabled, it will be connected between the osc1 and osc2 pins. in its typical configuration, the external oscillator requires five external components: 1. crystal, x 1 2. fixed capacitor, c 1 3. tuning capacitor, c 2 (can also be a fixed capacitor) 4. feedback resistor, r b 5. series resistor, r s (included in the diagram to follow stri ct pierce oscillator guidelines and may not be required for all ranges of operation, especially wi th high frequency crystals). refer to the crystal manufacturer?s data for more information. c 1 c 2 r b x 1 r s * *r s can be 0 (shorted) when used eclk internal to mcu external components required for external crystal use only osc1 osc2 amplifier input path with higher-frequency crystals. r efer to manufacturer?s data. extslow external clock generator name name name name configuration register bit top level signal register bit module signal ecgon stop functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 65 6.3.3.2 external clock input path the external clock input path is the means by which the microcontroller uses an external clock source. the input to the path is the osc1 pin and the output is the external clock (eclk). the path, which contains input buffering, is enabled when the ecgon bit is set and stop mode is not enabled. 6.3.4 clock m onitor circuit the icg contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (eclk) and the internal clock (iclk) to deter mine if either clock source has failed based on these conditions: either iclk or eclk has stopped. the frequency of ibase < fr equency eref divided by 4 the frequency of eclk < frequency of iref divided by 4 using the clock monitor requires both clocks to be active (ecgon and icgon are both set). to enable the clock monitor, both clocks must also be stable (ecgs and icgs both set). this is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable note although the clock monitor can be enabled only when the both clocks are stable (icgs or ecgs is set), the clock monitor will remain enabled if one of the clocks goes unstable. the clock monitor only works if the external slow (extslow) bit in the configuration register is properly def ined with respect to the external frequency source. the clock monitor circuit, shown in figure 6-5 , contains these blocks: clock monitor reference generator internal clock activity detector external clock activity detector 6.3.4.1 clock monitor reference generator the clock monitor uses a reference based on one clock source to monitor the other clock source. the clock monitor reference generator generates the external reference clock (eref) based on the external clock (eclk) and the internal reference clock (iref) based on the internal clock (iclk). to simplify the circuit, the low-frequency base clock (ibase) is used in place of iclk bec ause it always operates at or near 307.2 khz. for proper operation, eref must be at least twice as slow as ibase and iref must be at least twice as slow as eclk. to guarantee that iref is slower than eclk and er ef is slower than ibase, one of the signals is divided down. which signal is divided and by how much is determined by t he external slow (extslow) bit in the configuration register, according to the rules in table 6-2 . note that each signal (ibase and eclk) is always divided by four. a longer divider is used on either ibase or eclk based on the extslow bit. note if extslow is not set according to the rules defined in table 6-2 , the clock monitor could switch clock sources unexpectedly. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 66 freescale semiconductor figure 6-5. clock monitor block diagram the long divider (divide by 4096) is also used as an external crystal stabilization divider. the divider is reset when the external clock generator is off (ecgen is clear). when the external clock generator is first turned on, the external clock generator stable bit (ecgs) will be clear. this condition automatically selects eclk as the input to the long divi der. the external stabilization cloc k (estbclk) will be eclk divided by 4096. this timeout allows the crystal to stabili ze. the falling edge of estbclk is used to set ecgs (ecgs will set after a full 16 or 4096 cycles). when ecgs is set, the divider returns to its normal function. estbclk may be generated by either ibase or eclk, but any clocking will reinforce only the set condition. if ecgs is cleared because the clock monitor determined that eclk was inactive, the divider will revert to a stabilization divider. since this will change the eref and iref divide ratios, it is important to turn the clock monitor off (cmon = 0) after inactivity is detected to ensure valid recovery. ioff cmon ficgs ibase icgen eref ioff icgs ibase extxtalen extslow ecgs ecgon eclk icgon eref estbclk iref estbclk iref ecgen eclk cmon ecgs eoff iclk activity detector eclk activity detector divider cmon eoff ecgs icgs ibase icgen eclk name name name name configuration register bit top level signal register bit module signal ecgon stop extslow functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 67 6.3.4.2 internal clock activity detector the internal clock activity detector looks for at least one falling edge on the low-frequency base clock (ibase) every time the external refe rence (eref) is low. since eref is less than half the frequency of ibase, this should occur every time. if it does not occur two consecutive ti mes, the internal clock inactivity indicator (ioff) is set. ioff will be cleared the next time there is a falling edge of ibase while eref is low. the internal clock stable bi t (icgs) is set when ibase is within appro ximately 5% of th e target 307.2 khz 25% for two consecutive measuremen ts. icgs is cleared when ibase is outside the 5% of the target 307.2 khz 25%, the internal clock generator is disabl ed (icgen is clear), or when ioff is set. 6.3.4.3 external clock activity detector the external clock activity detector looks for at leas t one falling edge on the external clock (eclk) every time the internal reference (iref) is low. since iref is less than half the frequency of eclk, this should occur every time. if it does not occur two consecutive ti mes, the external clock inactivity indicator (eoff) is set. eoff will be cleared the next time there is a falling edge of eclk while iref is low. the external clock stable bit (ecgs) is also generated in the external clock activity detector. ecgs is set on a falling edge of the external stabilization clock (estbclk). this will be 4096 eclk cycles after the external clock generator on bit (ecgon) is set. ecgs is cleared when the external clock generator is disabled (ecgon is clea r) or when eoff is set. 6.3.5 clock se lection circuit the clock selection circuit, shown in figure 6-6 , contains two clock switches which generate the oscillator output clock (cgmxclk) from either the internal cl ock (iclk) or the external clock (eclk). the clock selection circuit also contains a divide-by-two ci rcuit which creates the clock generator output clock (cgmout), which generates the bus clocks. 6.3.5.1 clock selection switch the clock select switch creates the oscillator outpu t clock (cgmxclk) from either the internal clock (iclk) or the external clock (eclk), based on the cl ock select bit (cs; set selects eclk, clear selects table 6-2. clock monitor reference divider ratios icgon ecgon ecgs extslow external frequency eref divider ratio eref frequency estbclk divider ratio estbclk frequency iref divider ratio iref frequency 0xxx u uuuuoff0 x00 x 0 off 0 off 0 u u xx0 x min 30 khz off 0 4096 (eclk) 1.875 khz 1*4 76.8 khz 25% max 8 mhz 500 khz xx1 0 min 1 mhz 128*4 1.953 khz 4096 (eclk) 244 hz 1*4 76.8 khz 25% max 8 mhz 15.63 khz 1.953 khz xx1 1 min 30 khz 1*4 7.5 khz 4096 (ibase) 75 hz 25% 16*4 4.8 khz 25% max 100 khz 25.0 khz u: unaffected; refer to section of table w here icgon or ecgon is set to x (don?t care) [ibase is always used as the internal frequen cy (307.2 khz).] internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 68 freescale semiconductor iclk). when switching the cs bit, both iclk and ec lk must be on (icgon and ecgon set). the clock being switched to must also be stable (icgs or ecgs set). figure 6-6. clock selection circuit block diagram 6.3.5.2 clock switching circuit to robustly switch between the internal clock (iclk) and the external clock (eclk), the switch assumes the clocks are completely asynchronous, so a synchr onizing circuit is required to make the transition (see figure 6-7 ). when the clock select bit is changed, the switch will continue to operate off the original clock for between 1 and 2 cycles as the select input transitions through one side of the synchronizer. next, the output will be held low for between 1 and 2 cycles of the new clock as the select input transitions through the other side. then the output starts switching at the new clock?s frequency. this transition guarantees that no glitches will be seen on the output even though the select input may change asynchronously to the clocks. the unpredictably of the transition peri od is a necessary result of the asynchronicity. figure 6-7. synchronizing clock switcher circuit diagram iclk eclk ioff eoff force_i force_e select output synchronizing clock switcher div2 name name name top level signal register bit module signal reset eclk eoff iclk ioff v ss cs cgmout cgmxclk force_i eclk eoff output dq ck dff qb select iclk dq ck dff qb dq ck dff qb dq ck dff qb force_e force_i = force internal; reset condition force_e = force external ioff usage notes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 69 the switch automatically selects iclk during reset. when the clock monitor is on (cmon is set) and it determines one of the clock sources is inactive (as indicated by the ioff or eoff signals), the circuit is forced to select the active clock. there are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected. however, the active side will not be selected until one to two clock cycles after the ioff or eoff signal transitions. 6.4 usage notes the icg has several features which can provide protection to the microcontroller if properly used. there are other features which can greatly simplify usage of the icg if certain techniques are employed. this section will describe several possible ways to use the icg and its features. these techniques are not the only ways to use the icg, and may not be optimum for all environments. in any case, these techniques should be used only as a template, and the user shou ld modify them according to the application?s requirements. these notes include: switching clock sources enabling the clock monitor using clock monitor interrupts quantization error in dco output switching internal clock frequencies nominal frequency settling time improving frequency settling time trimming frequency 6.4.1 switchin g clock sources switching from one clock source to another requi res both clock sources to be enabled and stable. a simple flow requires: 1. enable desired clock source 2. wait for it to become stable 3. switch clocks 4. disable previous clock source the key point to remember in this flow is that th e clock source cannot be switched (cs cannot be written) unless the desired clock is on and stable. a short assembly code example of how to employ this flow is shown in figure 6-8 . this code is for illustrative purposes only and does not represent valid syntax for any particular assembler. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 70 freescale semiconductor figure 6-8. code example for switching clock sources 6.4.2 enabling the clock monitor many applications require the clock monitor to dete rmine if one of the clock sources has become inactive, so the other can be used to recover from a poten tially dangerous situation. using the clock monitor requires both clocks to be active (ecgon and icgon both set). to enable the clock monitor, both clocks also must be stable (ecgs and icgs both set). this is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable. enabling the clock monitor and clock monitor inte rrupts requires a flow similar to this flow: 1. enable the alternate clock source 2. wait for both clock sources to be stable 3. switch to the desired clock source if necessary 4. enable the clock monitor 5. enable clock monitor interrupts these events must happen in sequence. a short assembly code example of how to employ this flow is shown in figure 6-9 . this code is for illustrative purposes only and does not represent valid syntax for any particular assembler. figure 6-9. code example for enabling the clock monitor ;clock switching code example ;this code switches from internal to external clock ;clock monitor and interrupts are not enabled start lda #$13 ;mask for cs, ecgon, ecgs ;if switching from external to internal, mask is $0c. loop ** ** ;other code here, such as writing the cop, since ecgs may ;take some time to set sta icgcr ;try to set cs, ecgon and clear icgon. icgon will not ;clear until cs is set, and cs will not set until ;ecgon and ecgs are set. cmpa icgcr ;check to see if ecgs set, then cs set, then icgon clear ;clock monitor enabling code example ;this code turns on both clocks, selects the desired ; one, then turns on the clock monitor and interrupts start lda #$af ;mask for cmie, cmon, icgon, icgs, ecgon, ecgs ; if internal clock desired, mask is $af ; if external clock desired, mask is $bf ; if interrupts not desired mask is $2f int; $3f ext loop ** ** ;other code here, such as writing the cop, since ecgs ; and icgs may take some time to set. sta icgcr ;try to set cmie. cmie wont set until cmon set; cmon ; won?t set until icgon, icgs, ecgon, ecgs set. brset 6,icgcr,error ;verify cmf is not set cmpa icgcr ;check if ecgs set, then cmon set, then cmie set usage notes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 71 6.4.3 clock m onitor interrupts the clock monitor circuit can be used to recover from pe rilous situations such as crystal loss. to use the clock monitor effectively, these notes should be observed: enable the clock monitor and clock monitor interrupts. the first statement in the clock monitor interrupt service routine should be a read to the icg control register (icgcr) to verify that the clock monitor flag (cmf) is set. this is also the first step in clearing the cmf bit. never use bset or bclr instructions on the icg cr, as this may inadvertently clear cmf. only use the brset and brclr instructions to check the cmf bit and not to check any other bits in the icgcr. when the clock monitor detects inactivity on the se lected clock source (defined by the cs bit of the icg control register), the inactive clock is desel ected automatically and the remaining active clock is selected as the source for cgmxclk. the interrupt service routine can use the state of the cs bit to check which clock is inactive. when the clock monitor detects inactivity, t he application may have been subjected to extreme conditions which may have affected other circui ts. the clock monitor interrupt service routine should take any appropriate precautions. 6.4.4 quantization error in dco output the digitally controlled oscillator (dco) is comprised of three major sub-blocks: 1. binary weighted divider 2. variable-delay ring oscillator 3. ring oscillator fine-adjust circuit each of these blocks affects the clock period of the in ternal clock (iclk). since these blocks are controlled by the digital loop filter (dlf) outputs ddiv and dstg, the output of the dco can change only in quantized steps as the dlf increments or decrement s its output. the following sections describe how each block will affect the output frequency. 6.4.4.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk), whose clock period is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of the digital nature of the dco, the clock period of iclk will change in quantized steps. this will create a clock period difference or quantization e rror (q-err) from one cycle to the next. over several cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202% to 0.368%. the dependence of this error on the ddiv[3:0] value and the number of cycles the error is measured over is shown in table 6-3 . internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 72 freescale semiconductor 6.4.4.2 binary weighted divider the binary weighted divider divides the output of the ring oscillator by a power of 2, specified by the dco divider control bits (ddiv[3:0]). ddiv maximi zes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. when ddiv is %0000, the ring oscillator?s output is divided by 1. incrementing ddiv by one will double the period; decrementing ddiv will halve the period. the dlf cannot directly increment or decrement ddiv; ddiv is only incremented or decremented when an addition or subtraction to dstg carries or borrows. 6.4.4.3 variable-delay ring oscillator the variable-delay ring oscill ator?s period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three dco stage control bits (dstg[7:5]). a dstg[7:5] of %000 corresponds to 17 stage delays; dstg[7:5] of %111 corresponds to 31 stage delays. adjusting the dstg[5] bit has a 6.45% to 11.8% effect on the output frequency. this also corresponds to the size correction made when the frequency error is greater than 15%. the value of the binary weighted divider does not affect the relative change in output clock period for a given change in dstg[7:5]. 6.4.4.4 ring oscillator fine-adjust circuit the ring oscillator fine-adjust ci rcuit causes the ring oscillator to effectively operate at non-integer numbers of stage delays by operating at two different points for a variable number of cycles specified by the lower five dco stage control bits (dstg[4:0] ). for example, when dstg[7:5] is %011, the ring oscillator nominally operates at 23 stage delays. when ds tg[4:0] is %00000, the ring will always operate at 23 stage delays. when dstg[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles. like wise, when dstg[4:0] is %11111, the ring operates at 25 stage delays for 31 of 32 cycles and at 23 st age delays for one of 32 cycles. when dstg[7:5] is %111, similar results are achieved by including a vari able divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles. adjusting the dstg[0] bit has a 0.202% to 0.368% effect on the output clock period. this corresponds to the minimum size correction made by the dlf, and the inherent, long-term quantization error in the output frequency. table 6-3. quantization error in iclk ddiv[3:0] iclk cycles bus cycles iclk q-err %0000 (min) 4 1 1.61%?2.94% %0000 (min) 32 8 0.202%?0.368% %0001 4 1 0.806%?1.47% %0001 16 4 0.202%?0.368% %0010 4 1 0.403%?0.735% %0010 8 2 0.202%?0.368% %0011 4 1 0.202%?0.368% %0100 2 1 0.202%?0.368% %0101?%1001 (max) 1 1 0.202%?0.368% usage notes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 73 6.4.5 switching in ternal clock frequencies the frequency of the internal clock (iclk) may need to be changed for some applications. for example, if the reset condition does not provide the correct freq uency, or if the clock is slowed down for a low-power mode (or sped up after a low-power mode), the freq uency must be changed by programming the internal clock multiplier factor (n). the frequency of iclk is n times the frequency of ibase, which is 307.2 khz 25%. before switching frequencies by changing the n val ue, the clock monitor must be disabled. this is because when n is c hanged, the frequency of the low-freq uency base clock (ibase) will change proportionally until the digital loop filter has corrected the error. since the clock monitor uses ibase, it could erroneously detect an inactive clock. the clock monitor cannot be re-enabled until the internal clock is stable again (icgs is set). note there is no hardware mechanism to prevent changing bus frequency dynamically. be careful when changi ng bus frequency and consider the impact on the system. this flow is an example of how to change the clock frequency: 1. verify there is no clock monitor interrupt by reading the cmf bit. 2. turn off the clock monitor. 3. if desired, switch to the external clock (see 6.4.1 switching clock sources ). 4. change the value of n. 5. switch back to internal (see 6.4.1 switching clock sources ), if desired. 6. turn on the clock monitor (see 6.4.2 enabling the clock monitor ), if desired. 6.4.6 nominal fr equency settling time because the clock period of the internal clock (iclk) is dependent on the digital loop filter outputs (ddiv and dstg) which cannot change instantaneously, iclk will temporarily operate at an incorrect clock period when any of the operating condition changes. this happens whenever the part is reset, the icg multiply factor (n) is changed, the icg trim factor (trim) is changed, or the internal clock is enabled after inactivity (stop or disabl ed operation). the time that the iclk takes to adjust to the correct period is known as the settling time. settling time depends primarily on how many correcti ons it takes to change the clock period, and the period of each correction. since the corrections r equire four periods of the low-frequency base clock (4* ibase ), and since iclk is n (the icg multiply factor for the desired frequency) times faster than ibase, each correction takes 4*n* iclk . the period of iclk, however, will vary as the corrections occur. 6.4.6.1 settling to within 15% when the error is greater than 15%, the filter takes eight corrections to double or halve the clock period. due to how the dco increases or decreases the clock period, the total period of these eight corrections is approximately 11 times the period of the fastest correct ion. (if the corrections were perfectly linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly non-linear.) therefore, the total time it takes to double or halve the clock period is 44*n*t iclkfast . if the clock period needs more than doubled or halved, the same relationship applies, only for each time the clock period needs doubled, the total number of cycles doubles. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 74 freescale semiconductor that is, when transitioning from fast to slow: going from the initial speed to half speed takes 44*n*t iclkfast from half speed to quarter speed takes 88*n*t iclkfast going from quarter speed to eighth speed takes 176*n*t iclkfast , and so on. this series can be expressed as (2 x ?1)*44*n*t iclkfast , where x is the number of times the speed needs doubled or halved. since 2 x happens to be equal to iclkslow / iclkfast , the equation reduces to 44*n*( iclkslow - iclkfast ). note that increasing speed takes much longer than decreasing speed since n is higher. this can be expressed in terms of the initial clock period ( 1 ) minus the final clock period ( 2 ) as such: 6.4.6.2 settling to within 5% once the clock period is within 15% of the desired clock period, the filter starts making smaller adjustments. when between 15% and 5% error, each correction will adjust the clock period between 1.61% and 2.94%. in this mode, a maximum of eight corrections will be required to get to less than 5% error. since the clock period is relatively close to desired, each correction takes approximately the same period of time, or 4* ibase . at this point, the internal clock stabl e bit (icgs) will be set and the clock frequency is usable, although the erro r will be as high as 5%. the total time to this point is: 6.4.6.3 total settling time once the clock period is within 5% of the desired clock period, the filter starts making minimum adjustments. in this mode, each correction will adjust the frequency between 0.202% and 0.368%. a maximum of 24 corrections will be required to get to the minimum error. each correction takes approximately the same period of time or 4* ibase . added to the corrections for 15% to 5%, this makes 32 corrections (128* ibase ) to get from 15% to the minimum error. the total time to the minimum error is: the equations for 15 , 5 , and tot are dependent on the actual initial and final clock periods 1 and 2 , not the nominal. this means the variability in the ic lk frequency due to process, temperature, and voltage must be considered. additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. this mean s a worst case adjustment of up to 35% (iclk clock period tolerance plus 10%) must be added. this adjustment can be reduced with trimming. table 6-4 shows some typical values for settling time. table 6-4. typical settling time examples 1 2 n 15 5 tot 1/ (6.45 mhz) 1/ (25.8 mhz) 84 430 s 535 s 850 s 1/ (25.8 mhz) 1/ (6.45 mhz) 21 107 s 212 s 525 s 1/ (25.8 mhz) 1/ (307.2 khz) 1 141 s 246 s 560 s 1/ (307.2 khz) 1/ (25.8 mh z) 84 11.9 ms 12.0 ms 12.3 ms 15 abs 44n 1 2 ? () [] = 5 abs 44n 1 2 ? () [] 32 ibase + = tot abs 44n 1 2 ? () [] 128 ibase + = usage notes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 75 6.4.7 improving settling time the settling time of the internal clock generator can be vastly improved if an external clock source can be used during the settling time. when the internal clock gen erator is disabled (icgon is low), the ddiv[3:0] and dstg[7:0] bits can be written. then, when the internal clock generator is re-enabled, the clock period will automatically start at the point written in the ddiv and dstg bits. since a change in the ddiv and dstg bits only cause a change in the clock period relative to the starting point, the starting point must first be captured. the initial clock period can be expressed as in the next example, where x is a process, temperature, and volt age dependent constant and ddiv1 and dstg1 are the values of ddiv and dstg when operating at 1 . finding the new values for ddiv and dstg is easy if t he new clock period is a binary multiple or fraction of the original. in this case, dstg is unchanged and ddiv2 is ddiv1 + log 2 ( 2 / 1 ). if the new clock period is not a binary multiple or fraction of the original, both dstg and ddiv may need to change according to these equations: if dstg2 is greater than 255: the software required to do this is relatively simp le, since most of the math can be done before coding because the initial and final clock periods are known. an example of how to code this in assembly code is shown in figure 6-10 . this example is for illustrative pur poses only and does not represent a valid syntax for any particular assembler. 6.4.8 trimming fr equency on the inter nal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, will vary as much as 25% due to process, temperature, and voltage dependencies. these dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. the voltage and temperature dependencies have been designed to be a maximum of approximately 1% error. the process dependencies account for the rest. fortunately, for an individual part, the process depend encies are constant. an individual part can operate at approximately 2% variance from its unadjusted operating poi nt over the entire specification range of the application. if the unadjusted operating point c an be changed, the entire variance can be limited to 2%. 1 x 2 ddiv1 dstg1 ?? = dvfact int 2 1 ? () log 2 () log ----------------------------- = ddiv2 ddiv1 dvfact + = dsfact 2 1 ? () 2 ddiv2 ddiv1 ? () ---------------------------------------------------- = dstg2 dsfact dstg1 ? = ddiv2 ddiv2 1 + = dstg2 dstg2 2 -------------------- - = internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 76 freescale semiconductor figure 6-10. code example for writing ddiv and dstg the method of changing the unadjusted operating point is by changing the size of the capacitor. this capacitor is designed with 639 equally sized units. 384 of which are always connected. the remaining 255 units are put in by adjusting the icg trim factor (trim). the default value for trim is $80, or 128 units, making the default capacitor size 512. each un it added or removed will adjust the output frequency by about 0.195% of the unadjusted frequency (adding to trim will decrease frequency). therefore, the frequency of ibase can be changed to 25% of its unadjusted value, which is enough to cancel the process variability mentioned before. the best way to trim the internal clock is to use th e timer to measure the width of an input pulse on an input capture pin (this pulse must be supplied by the application and should be as long or wide as possible). considering the prescale value of the time r and the theoretical (zero error) frequency of the bus (307.2 khz *n/4), the error can be calculated. this error, expressed as a percentage, can be divided by 0.195% and the resultant factor added or subtracted from trim. this process should be repeated to eliminate any residual error. note it is recommended that the user preserve a copy of the contents of the icg trim register (icgtr) in non-volitale memory. address $7fef is reserved for an optional factory-determined value. consult with a local freescale representative for more information and availability of this option. ;ddiv and dstg modification code example ;changes ddiv and dstg according to the initial and ; desired clock period values ;requires icgon to be clear (disabled) ;user must previously calculate dvfact and stfact by ; the equations listed in the specification ;modifies x and a registers start lda icgcr ;verify icgon clear (this will require cmp #13 ; cmie,cmf,cmon,icgon,icgs clear and cs,ecgon,ecgs set) lda #dvfact ;add the ddiv factor (calculated before add icgdvr ; coding by the ddiv2 equation) sta icgdvr lda #stfact ;load the dstg factor (calculated before coding and ; multiplied by 128 to make it 0-255 for maximum precision ldx icgdsr ;load current stage register contents mul ;multiply factor times current value rola ;since factor was multiplied by 128, rolx ; result is x6-x0:a7, so put it all in x bcc store ;if result is >255, rolx will set carry rorx ; so divide result by two and inc ; add one to ddiv store stx icgdsr ;store value lda icgdvr ;test to see if ddiv too high or low cmp #09 ;valid range 0-9; too low is ff/fe; too high is 0a/0b bhi exit ;if ddiv is 0-9, you?re almost done lda #09 ;otherwise, maximize period and execute error code sta icgdvr low-power modes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 77 6.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.5.1 wait mode the icg remains active in wait mode. if enabled, the icg interrupt to the cpu can bring the mcu out of wait mode. in some applications, low-power consumption is desir ed in wait mode and a high-frequency clock is not needed. in these applications, reduce power consumpti on by either selecting a low-frequency external clock and turn the internal clock generator off, or reduce the bus frequency by minimizing the icg multiplier factor (n) before executing the wait instruction. 6.5.2 stop mode the icg is disabled in stop mode. upon execution of t he stop instruction, all icg activity will cease and the output clocks (cgmxclk and cgmout) will be held low. power consumption will be minimal. the stop instruction does not affect the values in t he icg registers. normal execution will resume after the mcu exits stop mode. 6.6 configuration register option one configuration register option affects the functio nality of the icg: extslow (slow external clock). all configuration register options will have a default setting. refer to chapter 3 configuration register (config) on how the configuration register is used. 6.6.1 extslow slow external clock (extslow), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 khz? 100 khz). when clear, extslow enables high frequency crystal operation (1 mhz to 8 mhz). extslow, when set, also configures the clock monitor to expect an external clock source that is slower than the low-frequency base clock (60 hz?307.2 khz) . when extslow is clear, the clock monitor will expect an external clock faster than the low-frequency base clock (307.2 khz?32 mhz). the default state for this option is clear. internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 78 freescale semiconductor 6.7 i/o registers the icg contains five registers, summarized in figure 6-11 . these registers are: icg control register, icgcr icg multiplier register, icgmr icg trim register, icgtr icg dco divider control register, icgdvr icg dco stage control register, icgdsr several of the bits in these registers have interacti on where the state of one bit may force another bit to a particular state or prevent another bit from being set or cleared. a summary of this interaction is shown in table 6-5 . addr.register name bit 7654321bit 0 $0036 internal clock generator control register (icgcr) see page 79. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: reset:00001000 $0037 internal clock generator multiplier register (icgmr) see page 81. read: r n6n5n4n3n2n1n0 write: reset:00010101 $0038 internal clock generator trim register (icgtr) see page 81. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 i cg dco divider control register (icgdvr) see page 82. read: rrrrddiv3ddiv2ddiv1ddiv0 write: reset:0000 uuuu $003a icg dco stage register (icgdsr) see page 82. read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write: reset: unaffected by reset = unimplemented r = reserved u = unaffected figure 6-11. icg i/o register summary i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 79 6.7.1 icg c ontrol register the icg control register (icgcr) contains the contro l and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits. cmie ? clock monitor interrupt enable bit this read/write bit enables clock monitor interrupts. an interrupt will occur when both cmie and cmf are set. cmie can be set when the cmon bit has been set for at least one cycle. cmie is forced clear when cmon is clear or during reset. 1 = clock monitor interrupts enabled 0 = clock monitor interrupts disabled table 6-5. icg module register bit interaction summary condition register bit results for given condition cmie cmf cmon cs icgon icgs ecgon ecgs n [6:0] trim[7:0] ddiv[3:0] dstg[7:0] reset 0 0 0 0 1 0 0 0 $15 $80 ? ? cmf = 1 ? (1) 1 ? 1 ? 1 ? uw uw uw uw cmon = 0 0 0 (0) ? ? ? ? ? ? ? ? ? cmon = 1 ? ? (1) ? 1 ? 1 ? uw uw uw uw cs = 0 ? ? ? (0) 1 ? ? ? ? ? uw uw cs = 1 ? ? ? (1) ? ? 1 ? ? ? ? ? icgon = 0 0 0 0 1 (0) 0 1 ? ? ? ? ? icgon = 1 ? ? ? ? (1) ? ? ? ? ? uw uw icgs = 0 us ? us uc ? (0) ? ? ? ? ? ? ecgon = 0 0 0 0 0 1 ? (0) 0 ? ? uw uw ecgs = 0 us ? us us ? ? ? (0) ? ? ? ? ioff = 1 ? 1* (1) 1 (1) 0 (1) ? uw uw uw uw eoff = 1 ? 1* (1) 0 (1) ? (1) 0 uw uw uw uw n = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? trim = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? ? register bit is unaffected by the given condition. 0, 1 register bit is forced clear or se t, respectively, in the given condition. 0*, 1* register bit is temporarily forced clear or set, respectively, in the given condition. (0), (1) register bit must be clear or set, respectively, for the given condition to occur. us, uc, uw register bit cannot be set, cleared, or written, respectively, in the given condition. address: $0036 bit 7654321bit 0 read: cmie cmf cmon cs icgon icgs ecgon ecgs write: reset:00001000 = unimplemented figure 6-12. icg control register (icgcr) internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 80 freescale semiconductor cmf ? clock monitor interrupt flag this read-only bit is set when the clock monitor deter mines that either iclk or eclk becomes inactive and the cmon bit is set. this bit is cleared by first re ading the bit while it is set, followed by writing the bit low. this bit is forced clear when cmon is clear or during reset. 1 = either iclk or eclk has become inactive. 0 = iclk and eclk have not become inactive since the last read of the icgcr or the clock monitor is disabled. cmon ? clock monitor on bit this read/write bit enables the clock monitor. cm on can be set when both iclk and eclk have been on and stable for at least one bus cycle (icgon, ecgon, icgs, and ecgs are all set). cmon is forced set when cmf is set, to avoid inadvertent clea ring of cmf. cmon is forced clear when either icgon or ecgon is clear or during reset. 1 = clock monitor output enabled 0 = clock monitor output disabled cs ? clock select bit this read/write bit determines which clock will gener ate the oscillator output clock (cgmxclk). this bit can be set when ecgon and ecgs have been set for at least one bus cycle and can be cleared when icgon and icgs have been set for at least one bus cycle. this bit is forced set when the clock monitor determines the internal clock (iclk) is inacti ve or when icgon is clear. this bit is forced clear when the clock monitor determines t hat the external clock (eclk) is inactive, when ecgon is clear, or during reset. 1 = external clock (eclk) sources cgmxclk 0 = internal clock (iclk) sources cgmxclk icgon ? internal clock generator on bit this read/write bit enables the internal clock generator. icgon can be cleared when the cs bit has been set and the cmon bit has been clear for at least one bus cycle. icgon is forced set when the cmon bit is set, the cs bit is clear, or during reset. 1 = internal clock generator enabled 0 = internal clock generator disabled icgs ? internal clock generator stable bit this read-only bit indicates when the internal clock generator has determined that the internal clock (iclk) is within about 5% of the desired value. this bit is forced clear when the clock monitor determines the iclk is inactive, when icgon is clear, when the icg multiplier factor is written, or during reset. 1 = internal clock is within 5% of the desired value. 0 = internal clock may not be within 5% of the desired value. ecgon ? external clock generator on bit this read/write bit enables the external clock generator. ecgon can be cleared when the cs and cmon bits have been clear for at least one bus cycl e. ecgon is forced set when the cmon bit or the cs bit is set. ecgon is forced clear during reset. 1 = external clock generator enabled 0 = external clock generator disabled i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 81 ecgs ? external clock generator stable bit this read-only bit indicates when at least 4096 exter nal clock (eclk) cycles have elapsed since the external clock generator was enabled. this is not an assurance of the stability of eclk but is meant to provide a start-up delay. this bit is forced clear when the clock monitor determines eclk is inactive, when ecgon is clear, or during reset. 1 = 4096 eclk cycles have elapsed since ecgon was set. 0 = external cock is unstable, inactive, or disabled. 6.7.2 icg multiplier register n6?n0 ? icg multiplier factor bits these read/write bits change the multiplier used by the internal clock generator. the internal clock (iclk) will be (307.2 khz 25%) * n. a value of $00 in this register is interpreted the same as a value of $01. this register cannot be wr itten when the cmon bit is set. reset sets this factor to $15 (decimal 21) for default frequency of 6.45 mhz 25% (1.613 mhz 25% bus). 6.7.3 icg trim register trim7?trim0 ? icg trim factor bits these read/write bits change the size of the internal capacitor used by the internal clock generator. by testing the frequency of the internal clock and increm enting or decrementing this factor accordingly, the accuracy of the internal clock can be improved to 2%. incrementing this register by one decreases the frequency by 0.195 percent of the unadjusted val ue. decrementing this register by one increases the frequency by 0.195%. this register cannot be wr itten when the cmon bit is set. reset sets these bits to $80, centering the range of possible adjustment. note it is recommended that the user preserve a copy of the contents of the icg trim register (icgtr) in non-volitale memory. address $7fef is reserved for an optional factory-determined icg trim value. consult with a local freescale representative for more information and availability of this option. address: $0037 bit 7654321bit 0 read: r n6n5n4n3n2n1n0 write: reset:00010101 r = reserved figure 6-13. icg multiplier register (icgmr) address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 6-14. icg trim register (icgtr) internal clock gene rator module (icg) mc68hc908rk2 data sheet, rev. 5.1 82 freescale semiconductor 6.7.4 icg dco divider register ddiv3?ddiv0 ? icg dco divider control bits these bits indicate the number of divide-by-twos ( ddiv) that follow the digitally controlled oscillator. incrementing ddiv will add another divide-by-two , doubling the period (halving the frequency). decrementing has the opposite effect. ddiv cannot be written when icgon is set to prevent inadvertent frequency shifting. when icgon is set, ddiv is controlled by the digital loop filter. the range of valid values for ddiv is from $0 to $9. va lues of $a?$f are interpreted the same as $9. since the dco is active during reset, reset has no effect on dstg and the value may vary. 6.7.5 icg dco stage register dstg7?dstg0 ? icg dco stage control bits these bits indicate the number of stages dstg ( above the minimum) in the digitally controlled oscillator. the total number of stages is approxima tely equal to $1ff, so changing dstg from $00 to $ff will approximately double the period. incrementing dstg will in crease the period (decrease the frequency) by 0.202% to 0.368% (decrementing has the opposite effect). dstg cannot be written when icgon is set to prevent inadvertent frequenc y shifting. when icgon is set, dstg is controlled by the digital loop filter. since t he dco is active during reset, reset has no effect on dstg and the value may vary. address: $0039 bit 7654321bit 0 read: rrrrddiv3ddiv2ddiv1ddiv0 write: reset:0000 uuuu r = reserved u = unaffected figure 6-15. icg dco divider register (icgdvr) address: $003a bit 7654321bit 0 read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write: reset: unaffected by reset figure 6-16. icg dco stage register (icgdsr) mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 83 chapter 7 keyboard/external interrupt module (kbi) 7.1 introduction this section describes the ma skable external interrupt (irq ) input and six independently maskable keyboard wakeup interrupt pins. 7.2 features features of the kbi include: dedicated external interrupt pin (irq ) six keyboard interrupt pins with separate ke yboard interrupt enable bits and one keyboard interrupt mask internal pullup resistor hysteresis buffer programmable edge-only or edge- and level-interrupt sensitivity automatic interrupt acknowledge 7.3 functional description this section provides a functional description of the keyboard/external interrupt module (kbi). 7.3.1 external interrupt a logic 0 applied to the external interrupt pin (irq ) can latch a cpu interrupt request. figure 7-2 shows the structure of the external (irq ) interrupt of the kbi module. a logic 0 applied to one or more of the keyboard interrupt pins can latch a cpu interrupt request. figure 7-5 shows the structure of the keyboard interrupts of the kbi module see figure 7-3 for a summary of the interrupt and keyboard input/output (i/o) registers. interrupt signals on the irq pin are latched into the irq latch. keyboard interrupts are latched in the keyboard interrupt latch. an interrupt latch remains set until one of these actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears irq latch and keyboard interrupt latch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (intkbscr). writing a 1 to the acki bit clears the irq latch. writing a 1 to the ackk bit clears the keyboard interrupt latch. reset ? a reset automatically clears both interrupt latches. keyboard/external inte rrupt module (kbi) mc68hc908rk2 data sheet, rev. 5.1 84 freescale semiconductor figure 7-1. block diagram highlighting kbi block and pins system integration module computer operating properly module security module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 32 bytes user flash ? 2031 bytes user ram ? 128 bytes monitor rom ? 768 bytes user flash vector space ? 14 bytes keyboard/interrupt module power internal bus ptb ddrb power-on reset module low-voltage inhibit module 2-channel timer module pta ddra software selectable internal oscillator module ptb5 ptb4/tch1 ptb3/tclk ptb2/tch0 ptb1 ptb0/mclk pta7 (2) pta6/kbd6 (2) (3) pta5/kbd5 (2) (3) pta4/kbd4 (2) (3) pta3/kbd3 (2) (3) pta2/kbd2 (2) (3) pta1/kbd1 (2) (3) pta0 (2) osc2 osc1 rst (1) irq (1) v dd v ss 1. pin contains integrated pullup resistor 2. high current sink pin 3. pin contains software selectable pullup resistor functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 85 figure 7-2. irq block diagram the irq pin and keyboard interrupt pins are falling-edge triggered and are software-configurable to be both falling-edge and low-level triggered. the modei and modek bits in the intkbscr controls the triggering sensitivity of the irq pin and keyboard interrupt pins. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of these occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch, the modei and modek control bits, thereby clearing the interrupt even if the pin stays low. addr.register name bit 7654321bit 0 $001a irq and keyboard status and control register (intkbscr) see page 90. read: irqf 0 imaski modei keyf 0 imaskk modek write: r acki r ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 91. read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 0 write: reset:00000000 = unimplemented r = reserved figure 7-3. irq and keyboard i/o register summary acki imaski dq ck clr irq high interrupt to mode select logic irq latch request irq v dd modei voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus v dd keyboard interrupt request irq/keyboard interrupt request internal pullup device reset keyboard/external inte rrupt module (kbi) mc68hc908rk2 data sheet, rev. 5.1 86 freescale semiconductor when set, the imaski and imaskk bits in the intkbscr masks all extern al interrupt requests. a latched interrupt request is not presented to the interrupt prio rity logic unless the corre sponding imask functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 87 7.3.2 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the modei bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with modei set, both of t hese actions must occur to clear the irq latch: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the acki bit in the irq and keyboard status a nd control register (intkbscr). the acki bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the acki bit can also prevent spurious interrupts due to noise. setting acki does not affect subsequent transitions on the irq pin. a falling edge on irq that occurs after writing to the acki bit latches another interrupt request. if the irq mask bit, imask i, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq latch remains set. the vector fetch or software clear and the return of the irq pin to logic 1 can occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the modei control bit, thereby clearing the interrupt even if the pin stays low. if the modei bit is clear, the irq pin is falling-edge sens itive only. with modei clear, a vector fetch or software clear immediately clears the irq latch.the ir qf bit in the intkbscr register can be used to check for pending interrupts. the irqf bit is not affe cted by the imaski bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 7.3.3 kbi module duri ng break interrupts the system integration module (sim ) controls whether the irq or keyboard interrupt latchs can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. see 10.7.3 sim break flag control register . to allow software to clear the irq or keyboard latchs during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the acki or ackk bits in the irq and ke yboard status and control register during the break state has no effect on the irq or keyboard latchs. 7.3.4 keyboard interrupt pins writing to the kbie6?kbie1 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches an irq/keyboard interrupt request. keyboard/external inte rrupt module (kbi) mc68hc908rk2 data sheet, rev. 5.1 88 freescale semiconductor figure 7-5. keyboard interrupt block diagram an irq/keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of these actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control regi ster (intkbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of all enabled keyboard interrupt pins to logic 1. as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. kb1ie kb6ie . . . keyboard interrupt dq ck clr v dd modek imaskk keyboard interrupt latch request vector fetch decoder ackk internal bus reset kbd6 kbd1 synchronizer keyf irq interrupt request irq/keyboard interrupt request to pullup enable to pullup enable low-power modes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 89 reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the irq and keyboard st atus and control register can be used to see if a pending interrupt exists. the keyf bit is not affect ed by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bit (kbie keyboard/external inte rrupt module (kbi) mc68hc908rk2 data sheet, rev. 5.1 90 freescale semiconductor 7.5 i/o registers these registers control and monitor operation of the keyboard/external interrupt module: irq and keyboard status and control register (intkbscr) keyboard interrupt enable register (kbier) 7.5.1 irq and k eyboard status and control register the irq and keyboard status and control register (intkbscr) controls and monitors operation of the keyboard/external interrupt module. the intkbscr has these functions: flags the keyboard interrupt requests acknowledges the keyboard interrupt requests masks the keyboard interrupt requests shows the state of the irq interrupt flag clears the irq interrupt latch masks the irq interrupt request controls the triggering sensitivity of the keyboard and irq interrupt pins irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending acki ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. acki always reads as 0. reset clears acki. imaski ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imaski. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled modei ? irq triggering sensitivity bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears modei. 1 = irq interrupt requests on falling edges and low levels 0 = interrupt requests on falling edges only keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $001a bit 7654321bit 0 read: irqf 0 imaski modei keyf 0 imaskk modek write: r acki r ackk reset:00000000 r= reserved figure 7-6. irq and keyboard status and control register (intkbscr) i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 91 ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 7.5.2 keyboard inte rrupt enable register the keyboard interrupt enable register (intkbier) enable s or disables each port a pin to operate as a keyboard interrupt pin. kbie6?kbie1 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. these bits also enable the corresponding internal pullup resistor which is enabled only when the bit is set. reset clears the keyboard interrupt enable register. 1 = pax pin enabled as keyboard interrupt pin and corresponding internal pullup resistor enabled 0 = pax pin not enabled as keyboard interrupt pin and corresponding internal pullup resistor disabled note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. address: $001b bit 7654321bit 0 read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 0 write: reset:00000000 = unimplemented figure 7-7. keyboard interrupt enable register (intkbier) keyboard/external inte rrupt module (kbi) mc68hc908rk2 data sheet, rev. 5.1 92 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 93 chapter 8 low-voltage inhibit (lvi) 8.1 introduction the low-voltage inhibit (lvi) module monitors the voltage on the v dd pin and will set a low voltage sense bit when v dd voltage falls to the lvi sense voltage . the lvi will force a reset when the v dd voltage falls to the lvi trip voltage. 8.2 features features of the lvi module include: detects two levels of low-voltage condition: ? low-voltage detection ? low-voltage reset user-configurable for stop mode 8.3 functional description figure 8-1 shows the structure of the lvi module. the lvi module contains a bandgap reference circuit and two comparators. the lvi monitors v dd voltage during normal mcu operation. when enabled, the lvi module generates a reset when v dd falls below the v lvr threshold. figure 8-1. lvi module block diagram in addition to forcing a reset condition, the lvi module has a second circuit dedicated to low-voltage detection. when v dd falls below v lvs , the output of the low-voltage comparator asserts the lowv flag in the lvi status register (lvisr). in applications that require detecting low batteries, software can monitor by polling the lowv bit. dead detector stop instruction v dd > v lvr = 0 v dd v lvr = 1 v dd reset battery weak detector battery lowv v dd > v lvs = 0 v dd v lvs = 1 lowv flag v dd digital filter cgmxclk lvi stop bit in configuration register lvi pwr bit in configuration register lvirst bit in configuration register lvitrip low-voltage inhibit (lvi) mc68hc908rk2 data sheet, rev. 5.1 94 freescale semiconductor 8.3.1 false trip protection the v dd pin level is digitally filtered to reduce false dead battery detection due to power supply noise. for the lvi module to reset due to a low-power supply, v dd must remain at or below the v lvr level for a minimum 32?40 cgmxclk cycles. see table 8-1 . 8.3.2 short stop recovery option the lvi has an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 cgmxclk cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery conf iguration option, the 32 cgmxclk delay must be greater than the lvi turn on time to avoid a period in startup where the lvi is not protecting the mcu. note the lvi is enabled automatically after reset or stop recovery, if the lvistop of the config register is set. see chapter 3 configuration register (config) . 8.4 lvi status register the lvi status register flags v dd voltages below thev lvr and v lvs levels. lviout ? lvi output bit the read-only flag becomes set when the v dd voltage falls below the v lvr voltage for 32 to 40 cgmxclk cycles. reset clears the lviout bit. lowv? lvi low indicator bit this read-only flag becomes set when the lvi is detecting v dd voltage below the v lvs threshold. table 8-1. lowv bit indication v dd result at level: for number of cgmxclk cycles: v dd > v lvr any filter counter remains clear v dd < v lvr < 32 cgmxclk cycles no reset, continue counting cgmxclk v dd < v lvr between 32 & 40 cgmxclk cycles lvi may generate a reset after 32 cgmxclk v dd < v lvr > 40 cgmxclk cycles lvi is guaranteed to generate a reset address: $fe0f bit 7654321bit 0 read:lviout0lowv00000 write: reset:00000000 = unimplemented figure 8-2. lvi status register (lvisr) lvi interrupts mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 95 8.5 lvi interrupts the lvi module does not generate cpu interrupt requests. 8.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 8.6.1 wait mode the lvi module remains active in wait mode. the lvi module can generate a reset if a v dd voltage below the v lvr voltage is detected. 8.6.2 stop mode the lvi can be enabled or disabled in stop mode by setti ng the lvistop bit in the config register. see chapter 3 configuration register (config) . note to minimize stop i dd, disable the lvi in stop mode. low-voltage inhibit (lvi) mc68hc908rk2 data sheet, rev. 5.1 96 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 97 chapter 9 input/output (i/o) ports 9.1 introduction fourteen bidirectional input/output ( i/o) pins form two parallel ports in the 20-pin ssop/soic package. all i/o pins are programmable as inputs or outpu ts. port a bits pta6?pta1 have keyboard wakeup interrupts and internal pullup resistors. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 9.2 port a port a is an 8-bit special function port that shares six of its pins with the keyboard interrupt module (kbd). pta6?pta1 contain pullup resistors enabled when the port pin is enabled as a keyboard interrupt. port a pins are also high-current port pins with 3-ma sink capabilities. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 98. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 100. read: ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 98. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 100. read: mclken 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 9-1. i/o port register summary input/output (i/o) ports mc68hc908rk2 data sheet, rev. 5.1 98 freescale semiconductor 9.2.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd[6:1] ? keyboard wakeup pins the keyboard interrupt enable bits, kbie[6:1], in the keyboard interrupt control register enable the port a pin as external interrupt pins and related internal pullup resistor. see chapter 7 keyboard/external interrupt module (kbi) . note the enabling of a keyboard interrupt pin will overide the corresponding definition of the pin in the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 9.2.2 data dir ection register a data direction register a (ddra) determines whether eac h port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the co rresponding port a pin; a 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternate function: kbd6 kbd5 kbd4 kbd3 kbd2 kbd1 = unimplemented figure 9-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 9-3. data direction register a (ddra) port b mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 99 figure 9-4 shows the port a i/o logic. when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 9-1 summarizes the operation of the port a pins. figure 9-4. port a i/o circuit note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 9.3 port b port b is a 6-bit special function port that shares th ree of its pins with the timer (tim) module and one with the buffered internal bus clock mclk. table 9-1. port a pin functions kbie (2) bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 1x x (1) input, v dd (4) ddra[7:0] pin pta[7:0] (3) 00x input, hi-z (5) ddra[7:0] pin pta[7:0] (3) 0 1 x output ddra[7:0] pta[7:0] pta[7:0] notes: 1. x = don?t care 2. keyboard interrupt enable bit (see 7.5.2 keyboard interrupt enable register ) 3. writing affects data register, but does not affect input. 4. i/o pin pulled up to v dd by internal pullup device 5. hi-z = high impedance read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ddrax ptax internal data bus ptax v dd kbie x internal pullup device input/output (i/o) ports mc68hc908rk2 data sheet, rev. 5.1 100 freescale semiconductor 9.3.1 port b data register the port b data register (ptb) contains a data latch for each of the six port b pins. ptb[5:0] ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. tch1 ? timer channel i/o bit the ptb4/tch1 pin is the tim channel 1input capture/output compare pin. the edge/level select bits, els1b:els1a, determine whether the ptb4/tch1 pi n is a timer channel i/o or a general-purpose i/o pin. see chapter 11 timer interface module (tim) . tch0 ? timer channel i/o bit the ptb2/tch0 pin is the tim channel 0 input capt ure/output compare pin. the edge/level select bits, els0b:els0a, determine whether the ptb2/tch0 pi n is a timer channel i/o or a general-purpose i/o pin. see chapter 11 timer interface module (tim) . tclk ? timer clock the ptb3/tclk pin is the external clock input for tim. the prescaler select bits, ps[2:0], select ptb3/tclk as the tim clock input. (see 11.8.1 tim status and control register .) when not selected as the tim clock, ptb3/tclk is available for general-purpose i/o. mclk ? bus clock the bus clock (mclk) is driven out of pin ptb0 /mclk when enabled by the mclken bit in port b data direction register bit 7. 9.3.2 data direction register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. address: $0001 bit 7654321bit 0 read: ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate functions: tch1 tclk tch0 mclk = unimplemented figure 9-5. port b data register (ptb) address: $0005 bit 7654321bit 0 read: mclken 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 9-6. data direction register b (ddrb) port b mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 101 mclken ? mclk enable bit this read/write bit enables mclk to be an output si gnal on ptb0. if mclk is enabled, ptb0 is under the control of mclken. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled ddrb[5:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[5:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 9-7 shows the port b i/o logic. figure 9-7. port b i/o circuit when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 9-2 summarizes the operation of the port b pins. table 9-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x input, hi-z ddrb[7] ddrb[5:0] pin ptb[5:0] (1) 1 x output ddrb[7] ddrb[5:0] ptb[5:0] ptb[5:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output (i/o) ports mc68hc908rk2 data sheet, rev. 5.1 102 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 103 chapter 10 system integration module (sim) 10.1 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim controls all mcu activities. the sim is a system state controller that coordinates cpu and exception timing. a block diagr am of the sim is shown in figure 10-2 . figure 10-1 is a summary of the sim input/output (i/o) registers. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 115. read: rrrrrr sbsw r write: see note reset: 0 note: writing a 0 clears sbsw $fe01 sim reset status register (srsr) see page 116. read: por pin cop ilop ilad 0 lvi 0 write: por:1xxxxxxx $fe02 sim break flag control register (sbfcr) see page 117. read: bcferrrrrrr write: reset:00000000 = unimplemented r = reserved x = indeterminate figure 10-1. sim i/o register summary system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 104 freescale semiconductor figure 10-2. sim block diagram table 10-1 shows the internal signal names used in this section. table 10-1. signal name conventions signal name description cgmxclk selected clock source from internal clock generator module (icg) cgmout clock output from icg module (bus clock = cgmout divided by two) iclk output from internal clock generator eclk external clock source iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to icg) cgmout (from icg) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from icg) 2 sim bus clock control and generation mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 105 10.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an in coming clock, cgmout, as shown in figure 10-3 . this clock can come from either an external oscillator or from the internal clock generator (icg) module. 10.2.1 bus timing in user mode , the internal bus frequency is either the crysta l oscillator output (eclk) divided by four or the icg output (iclk) divided by four. 10.2.2 clock startup fr om por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals ar e inactive and held in an inactive phase until after 4096 cgmxclk cycles. the rst pin is driven low by the sim during this entire period. the bus clocks start upon completion of the timeout. figure 10-3. icg clock signals 10.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 10.6.2 stop mode .) in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. icg cgmxclk 2 bus clock generators sim icg sim counter ptb3 monitor mode clock select circuit iclk cs 2 a b s* cgmout *when s = 1, cgmout = b user mode generator eclk system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 106 freescale semiconductor 10.3 reset and s ystem initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 10.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 10.7 sim registers .) 10.3.1 external pin reset the rst pin circuit includes an internal pullu p device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. figure 10-4 shows the relative timing of an external reset recovery. figure 10-4. external reset recovery timing iab pc vect h vect l cgmout pulled low external rst pulled high external reset and system initialization mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 107 10.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. (see figure 10-5 .) an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. (see figure 10-6 .) note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 10-5 . figure 10-5. internal reset timing figure 10-6. sources of internal reset the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 10.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. another 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 108 freescale semiconductor figure 10-7. por recovery 10.3.2.2 computer operating properly (cop) reset the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr) if the copd bit in the config register is at 0. see chapter 4 computer operating properly module (cop) . 10.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the configuration register (config) is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. 10.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 10.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v lvr voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config register are at 0. the rst pin will be held low until the sim counts 4096 cgmxclk cycles after v dd rises above v lvr + h lvr . another 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. see chapter 8 low-voltage inhibit (lvi) . porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff sim counter mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 109 10.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clock ed by the falling edge of cgmxclk. 10.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the internal clock generation module (icg) to drive the bus clock state machine. 10.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxcl k cycles. this is ideal for appl ications using c anned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. 10.4.3 sim counter and reset states external reset has no effect on the sim counter. see 10.6.2 stop mode for details. the sim counter is free-running after all reset states. see 10.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 10.5 program exception control normal, sequential program execution can be changed in three different ways: 1. interrupts: a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 110 freescale semiconductor 10.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 10-8 shows interrupt entry timing. figure 10-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). (see figure 10-10 .) figure 10-8 . interrupt entry figure 10-9. interrupt recovery idb r/w dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[ 1 5 : 8 ] x a ccr v data h v data l opcode i bit module interrupt idb r/w sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [15:8] pc ? 1 [ 7: 0] opcode operand i bit module interrupt program exception control mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 111 figure 10-10. interrupt processing no no no yes no no yes yes as many interrupts i bit set? from reset break interrupt? i bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 112 freescale semiconductor 10.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 10-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m68hc05, m6805, and m146805 families the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. figure 10-11 . interrupt recognition example 10.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine low-power modes mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 113 10.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 10.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (see 12.2 break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 10.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 10.6 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described here. both stop and wait clear the interr upt mask (i) in the condi tion code register, allowing interrupts to occur. 10.6.1 wait mode in wait mode, the cpu clocks are inactive while one set of peripheral clocks continues to run. figure 10-12 shows the timing for wait mode entry. figure 10-12. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 114 freescale semiconductor a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the mask option register is 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 10-13 and figure 10-14 show the timing for wait recovery. figure 10-13. wait recovery from interrupt or break 10.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also caus es an exit from stop mode. figure 10-14. wait recovery from internal reset the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is sele ctable using the ssrec bit in the config register. if ssrec is set, stop recovery is reduced from t he normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications usin g canned oscillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt orr break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles sim registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 115 the sim counter is held in reset from the executi on of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 10-15 shows stop mode entry timing. figure 10-15. stop mode entry timing figure 10-16. stop mode recovery from interrupt or break 10.7 sim registers the sim has three memory mapped registers: sim break status register, sbsr sim reset status register, srsr sim break flag control register, sbfcr 10.7.1 sim break st atus register the sim break status register (sbsr) contains a flag to indicate that a break caus ed an exit from stop or wait mode. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: see note reset: 0 r = reserved note: writing a 0 clears sbsw. figure 10-17. sim break status register (sbsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 116 freescale semiconductor sbsw ? sim break stop/wait bit sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. wr iting 0 to the sbsw bit clears it. 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. 10.7.2 sim reset status register this register contains six flags that show the source of the last reset. the status register will clear automatically after reading it. a power-on reset sets the por bit. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:1xxxxxxx = unimplemented x = indeterminate figure 10-18. sim reset status register (srsr) sim registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 117 10.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe02 bit 7654321bit 0 read: bcferrrrrrr write: reset:00000000 r= reserved figure 10-19. sim break flag control register (sbfcr) system integration module (sim) mc68hc908rk2 data sheet, rev. 5.1 118 freescale semiconductor mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 119 chapter 11 timer interface module (tim) 11.1 introduction this section describes the timer interface module (t im). the tim is a 2-channel timer that provides a timing reference with input capture, output co mpare, and pulse-width-m odulation (pwm) functions. figure 11-2 is a block diagram of the tim. 11.2 features features of the tim include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pwm signal generation programmable tim clock input: ? 7-frequency internal bus clock prescaler selection ? external tim clock input (bus frequency 2 maximum) free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 11.3 pin name conventions the tim module shares pins with th ree port b input/output (i/o) port pins. the full names of the tim i/o pins and generic pin names are listed in table 11-1 . table 11-1. pin name conventions tim generic pin names: tch0 tch1 tclk full tim pin names: ptb2/tch0 ptb4/tch1 ptb3/tclk timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 120 freescale semiconductor figure 11-1. block diagram highlighting tim block and pins 11.4 functional description figure 11-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a mo dulo up-counter. the tim counter provides the timing reference for the input capture and output compare f unctions. the tim counter modulo registers, tmodh and tmodl, control the modulo value of the tim c ounter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels are programmable independently as input capture or output compare channels. refer to figure 11-3 for a summary of the tim i/o registers. system integration module computer operating properly module security module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 32 bytes user flash ? 2031 bytes user ram ? 128 bytes monitor rom ? 768 bytes user flash vector space ? 14 bytes keyboard/interrupt module power internal bus ptb ddrb power-on reset module low-voltage inhibit module 2-channel timer module pta ddra software selectable internal oscillator module ptb5 ptb4/tch1 ptb3/tclk ptb2/tch0 ptb1 ptb0/mclk pta7 (2) pta6/kbd6 (2) (3) pta5/kbd5 (2) (3) pta4/kbd4 (2) (3) pta3/kbd3 (2) (3) pta2/kbd2 (2) (3) pta1/kbd1 (2) (3) pta0 (2) osc2 osc1 rst (1) irq (1) v dd v ss 1. pin contains integrated pullup resistor 2. high current sink pin 3. pin contains software selectable pullup resistor functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 121 figure 11-2. tim block diagram addr.register name bit 7654321bit 0 $0020 timer status and control register (tsc) see page 128. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (tcnth) see page 129. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer counter register low (tcntl) see page 129. read:bit 7654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (tmodh) see page 130. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 = unimplemented figure 11-3. tim i/o register summary prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a port tof toie inter- 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a logic rupt logic inter- rupt logic port logic inter- rupt logic ptb3/tclk ptb2/tch0 ptb4/tch1 internal timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 122 freescale semiconductor 11.4.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 11.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter into the tim channel registers, tchxh and tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.4.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests. $0024 timer counter modulo register low (tmodl) see page 130. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (tsc0) see page 131. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (tch0h) see page 134. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer channel 0 register low (tch0l) see page 134. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (tsc1) see page 131. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer channel 1 register high (tch1h)) see page 134. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (tch1l)) see page 134. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-3. tim i/o register summary (continued) functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 123 11.4.4 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 11.4.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered ch anges in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 11.4.5 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptb2/tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 11.4.6 pulse-widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pulse-width modulation (pwm) signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between over flows is the period of the pwm signal. as figure 11-4 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 124 freescale semiconductor the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 11.8.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50 percent. figure 11-4. pwm period and pulse width 11.4.7 unbuffered pw m signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.4.6 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. ptb2/tch0 period pulse width overflow overflow overflow output compare output compare output compare functional description mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 125 11.4.8 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. 11.4.9 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh and tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh and tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb and msxa. see table 11-3 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb and elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise . toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h and tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 126 freescale semiconductor clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is alr eady in and have no effect. the result is a 0 percent duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100 percent duty cycle output. (see 11.8.4 tim channel status and control registers .) 11.5 interrupts these tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f and ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu in terrupt requests are controlled by the channel x interrupt enable bit, chxie. 11.5.1 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 11.5.2 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 11.5.3 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.6 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 10.7.3 sim break flag control register . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the i/o signals mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 127 break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 11.7 i/o signals port b shares three of its pins with the tim. tclk can be used as an external clock input to the tim prescaler and the tim channel 0 i/o pin ptb2/tch0 and tim channel 1 i/o pin ptb4/tch1. 11.7.1 tim clock pin (tclk) tclk is an external clock input that can be the cloc k source for the tim counter instead of the prescaled internal bus clock. select the tclk input by writin g 1s to the three prescaler select bits, ps2?ps0. see 11.8.1 tim status and control register . the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 refer to 13.8 control timing . tclk is available as a general-purpose i/o pin w hen not used as the tim clock input. when the tclk pin is the tim clock input, it is an input regardless of the state of the ddrb3 bit in data direction register b. 11.7.2 tim channel i/ o pins (tch0 and tch1) the channel i/o pins are programm able independently as an input captur e pin or an output compare pin. tch0 and tch1 can be configured as buffered output compare or buffered pwm pins. 11.8 i/o registers these i/o registers control and monitor operation of the tim: tim status and control register, tsc tim control registers, tcnth and tcntl tim counter modulo registers, tmodh and tmodl tim channel status and control registers, tsc0 and tsc1 tim channel registers, tch0h, tch0l, tch1h, and tch1l 11.8.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock 1 + t su bus frequency timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 128 freescale semiconductor tof ? tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps2?ps0 ? prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 11-2 shows. reset clears the ps2?ps0 bits. address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-5. tim status and control register (tsc) i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 129 11.8.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 11-2. prescaler selection ps2?ps0 tim clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 tclk register name and address: tcnth?$0021 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 register name and address: tcntl?$0022 bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented figure 11-6. tim counter registers (tcnth and tcntl) timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 130 freescale semiconductor 11.8.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof ) becomes set, and the tim counter resumes counting from $0000 at the next clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. re set sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. register name and address: tmodh?$0023 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 register name and address: tmodl?$0024 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 11-7. tim counter modulo registers (tmodh and tmodl) i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 131 11.8.4 tim channel status and control registers each of the tim channel status and control registers (tsc0 and tsc1): flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 100 percent pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled register name and address: tsc0?$0025 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address: tsc1?$0028 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-8. tim channel status and control registers (tsc0 and tsc1) timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 132 freescale semiconductor msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 and tim channel 1 status and control registers. setting ms0b disables the tim channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. see table 11-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear , channel x is not connected to port b, and pin ptbx/tchx is available as a general-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare i/o registers mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 133 note before enabling a tim channel register for input capture operation, make sure that the ptb/tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 0, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 11-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100 per cent duty cycle level until the cycle after chxmax is cleared. figure 11-9. chxmax latency output overflow ptbx/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) mc68hc908rk2 data sheet, rev. 5.1 134 freescale semiconductor 11.8.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. register name and address: tch0h?$0026 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset register name and address: tch0l?$0027 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-10. tim channel 0 registers (tch0h and tch0l) register name and address: tch1h?$0029 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset register name and address: tch1l?$002a bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-11. tim channel 1 registers (tch1h and tch1l) mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 135 chapter 12 development support 12.1 introduction this section describes the break module, the moni tor read-only memory (mon), and the monitor mode entry methods. 12.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during break interrupts cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 12.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu th en loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 12-1 shows the structure of the break module. development support mc68hc908rk2 data sheet, rev. 5.1 136 freescale semiconductor figure 12-1. break module block diagram 12.2.1.1 flag protection during break interrupts the system integration module (sim) controls whethe r module status bits can be cleared during the break state. the bcfe bit in the sim break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 10.7.3 sim break flag control register and the break interrupts subsection for each module.) 12.2.1.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. addr.register name bit 7654321bit 0 $fe0c break address register high (brkh) see page 138. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) see page 138. read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (bscr) see page 137. read: brke brka 000000 write: reset:00000000 = unimplemented figure 12-2. i/o register summary iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] break break module (brk) mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 137 12.2.1.3 tim during break interrupts a break interrupt stops the timer counter. 12.2.1.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 12.2.2 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 12.2.2.1 wait mode if enabled, the break module is active in wait mode. 12.2.2.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 12.2.3 break module registers these registers control and monitor operation of the break module: break status and control register, bscr break address register high, brkh break address register low, brkl 12.2.3.1 break status and control register the break status and control register (bscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writin g a 0 to it before exiting the break routine. 1 = break address match 0 = no break address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 12-3. break status and control register (bscr) development support mc68hc908rk2 data sheet, rev. 5.1 138 freescale semiconductor 12.2.3.2 break address registers the break address registers contain the high and lo w bytes of the desired breakpoint address. reset clears the break address registers. 12.3 monitor module this subsection describes the monitor read-only memory (mon). the mon allows complete testing of the mcu through a single-wire interface with a host computer. features include: normal user-mode pin functionality one pin dedicated to serial communicati on between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer 9600 baud communication with host computer when using a 9.8304-mhz crystal execution of code in random-a ccess memory (ram) or flash flash security flash programming 12.3.1 functional description monitor rom receives and executes commands from a host computer. figure 12-5 shows a sample circuit used to enter monitor mode and communic ate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the mc68hc908rk2 has a flash security feature to prevent external viewing of the contents of flash. proper procedures must be followed to verify flash content. access to the flash is denied to unauthorized users of customer-specified software (see 12.3.2 security ). in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all comm unication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexi ng interface is required between pta0 and the host computer. pta0 is used in a wired-or c onfiguration and requires a pullup resistor. register name and address: brkh?$fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 register name and address: brkl?$fe0d read: bit 7654321bit 0 write: reset:00000000 figure 12-4. break address registers (brkh and brkl) monitor module mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 139 figure 12-5. monitor mode circuit + + + 10 m ? x1 v dd v tst mc145407 mc74hc125 68hc908rk2 rst irq osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 10 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 9.8304 mhz 10 k ? 10 k ? 5 6 + ptb0 ptb2 v dd 10 k ? development support mc68hc908rk2 data sheet, rev. 5.1 140 freescale semiconductor 12.3.1.1 monitor mode entry table 12-1 shows the pin conditions for entering monitor mode. enter monitor mode by either: executing a software interrupt instruction (swi), or applying a logic 0 and then a logic 1 to the rst pin note upon entering monitor mode, an interrupt stack frame plus a stacked h register will leave the stack pointer at address $00f9. once out of reset, the mcu waits for the host to send eight security bytes (see 12.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecutive 0s) to the host computer, indicating that it is ready to receive a command. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v tst (see chapter 13 electrical specifications is applied to either the irq pin or the rst pin. (see chapter 10 system integration module (sim) for more information on modes of operation.) t he icg module is bypassed in monitor mode as long as v tst is applied to the irq pin. rst does not affect the icg. table 12-2 is a summary of the differences between user mode and monitor mode. table 12-1. monitor mode entry irq pin ptb0 pin ptb2 pin pta0 pin cgmount (1) 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the clock select bit (cs) controls the source of cgmout. bus frequency v tst (2) 2. for v tst , see 13.6 3.0-volt dc electrical characteristics and 13.7 2.0-volt dc electrical char- acteristics . 101 table 12-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. see 13.6 3.0-volt dc electrical characteristics . $fefe $feff $fefc $fefd $fefc $fefd cgmxclk 2 ----------------------------- cgmout 2 -------------------------- monitor module mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 141 12.3.1.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. (see figure 12-6 and figure 12-7 .) the data transmit and receive rate is determined by the crystal. transmit and receive baud rates must be identical. figure 12-6. monitor data format figure 12-7. sample monitor waveforms 12.3.1.3 echoing as shown in figure 12-8 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 12-8. read transaction 12.3.1.4 break signal a start bit followed by nine low bits is a break signal. (see figure 12-9 .) when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 notes: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 3 = wait 1 bit time before sending next byte. 1, 2, 3 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 notes: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 3 = wait 1 bit time before sending next byte. 1, 2, 3 1, 2, 3 addr. high read read addr. high addr. low addr. low data echo sent to monitor result notes: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 3 = wait 1 bit time before sending next byte. 1 3 1 3 1 2 development support mc68hc908rk2 data sheet, rev. 5.1 142 freescale semiconductor figure 12-9. break transaction 12.3.1.5 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. figure 12-10. read transaction figure 12-11. write transaction 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop-bit delay before zero echo read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, 2 bit times monitor module mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 143 a brief description of each monitor mode command is given in table 12-3 through table 12-8 . table 12-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 12-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-by te order; low byte followed by data byte data returned none opcode $49 command sequence table 12-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo data return data from host development support mc68hc908rk2 data sheet, rev. 5.1 144 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. table 12-6. iwrite (indexed write) command description write to la st address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 12-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 12-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host monitor module mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 145 figure 12-12. stack pointer at monitor mode entry 12.3.1.6 baud rate with a 9.8304-mhz crystal, data is transferred between the monitor and host at 9600 baud. if a 14.7456-mhz crystal is used, the monitor baud rate is 9600. note while in monitor mode with v tst applied to irq , the mcu bus clock is always driven from the external clock. 12.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight consecutive security bytes that match the bytes at locations $fff6?$fffd. locat ions $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. if flash is unprogrammed, the eight security byte values to be sent are $00, the unprogrammed state of the flash. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pa0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. after the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes, but security remains bypassed regardless of the data that the host sends. if the received bytes do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading flash locations returns undefined data, and trying to execute code from flas h causes an illegal address reset. after the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. after receiving the eight security bytes from the hos t, the mcu transmits a break character signalling that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 development support mc68hc908rk2 data sheet, rev. 5.1 146 freescale semiconductor figure 12-13. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst 4096 + 32 cgmxclk cycles 24 cgmxclk cycles 1 3 1 1 2 1 break notes: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 3 = wait 1 bit time before sending next byte. 3 from host from mcu ($fff6) ($fff7) ($fffd) 256 cgmxclk cycles (one bit time) v dd irq see note note: any delay between rising irq and rising v dd will guarantee that the mcu bus is driven by the external clock. mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 147 chapter 13 electrical specifications 13.1 introduction this section contains electrical and timing specifications. 13.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 13.6 3.0-volt dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic (1) 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +3.6 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd , v ss , and pta7?pta0 i 15 ma maximum current for pins pta7?pta0 i pta7 ?i pta0 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ?55 to +150 c electrical specifications mc68hc908rk2 data sheet, rev. 5.1 148 freescale semiconductor 13.3 functional operating range 13.4 thermal characteristics characteristic symbol min max unit operating temperature range (1) 1. extended temperature range to be determined t a ?40 85 c operating voltage range v dd 1.8 3.6 v characteristic symbol value unit thermal resistance ssop (20 pin) soic (20 pin) ja 177 88 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 100 c 1.8-volt to 3.3-volt dc electrical characteristics mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 149 13.5 1.8-volt to 3.3-volt dc electrical characteristics characteristic (1) 1. parameters are design targets at v dd = 1.8 v to 3.3 v, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?1.2 ma) (i load = ?2.0 ma) v oh v dd ?0.3 v dd ?1.0 ? ? ? ? v output low voltage (i load = 1.2 ma) (i load = 3.0 ma) (i load = 3.0 ma) pta7?pta0 only v ol ? ? ? ? ? ? 0.3 1.0 0.3 v input high voltage, all ports, irq , osc1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage, all ports, irq , osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) (f op = 2.0 mhz) wait (4) (f op = 2.0 mhz) stop (5) 25 c ?40 c to 85 c 25 c with lvi enabled ?40 c to 85 c with lvi enabled 3. run (operating) i dd measured using internal clock generator module (f op = 2.0 mhz). v dd = 3.3 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on a ll outputs. all ports configured as inputs. c l = 20 pf. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using internal clock generator module, f op = 2.0 mhz. all inputs 0.2 v fr om rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf. osc2 capacitance linearly affects wait i dd . all ports configured as inputs. 5. stop i dd measured with no port pins sourcing current, all modules disabled except as noted. i dd ? ? ? ? ? ? ? ? 10 ? 50 ? 4.3 1.2 ? 100 ? 350 ma ma na na a a i/o ports high-impedance leakage current (6) 6. pullups and pulldowns are disabled. i il ?1 ? +1 a input current i in ?1 ? +1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) 7. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (8) 8. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate (9) 9. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ?8v pullup resistor, pta6?pta1, irq r pu 70 ? 120 k ? electrical specifications mc68hc908rk2 data sheet, rev. 5.1 150 freescale semiconductor 13.6 3.0-volt dc el ectrical characteristics characteristic (1) 1. parameters are design targets at v dd = 3.0 10%, v ss = 0 vdc, t a = ?40c to +85c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?2.0 ma) (i load = ?8.0 ma) v oh v dd ?0.3 v dd ?1.0 ? ? ? ? v output low voltage (i load = 2.0 ma) (i load = 6.5 ma) (i load = 5.0 ma) pta7?pta0 only v ol ? ? ? ? ? ? 0.3 1.0 0.3 v input high voltage, all ports, irq , osc1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage, all ports, irq , osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) (f op = 4.0 mhz) wait (4) (f op = 4.0 mhz) stop (5) 25 c ?40 c to 85 c 25 c with lvi enabled ?40 c to 85 c with lvi enabled 3. run (operating) i dd measured using internal clock generator module (f op = 4.0 mhz). v dd = 3.3 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on a ll outputs. all ports configured as inputs. c l = 20 pf. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using internal clock generator module, f op = 4.0 mhz. all inputs 0.2 v fr om rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf. osc2 capacitance linearly affects wait i dd . all ports configured as inputs. 5. stop i dd measured with no port pins sourcing current, all modules disabled except as noted. i dd ? ? ? ? ? ? ? ? 10 ? 50 ? 8.6 1.2 ? 100 ? 350 ma ma na na a a i/o ports high-impedance leakage current (6) 6. pullups and pulldowns are disabled. i il ?1 ? +1 a input current i in ?1 ? +1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) 7. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (8) 8. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate (9) 9. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ?8v pullup resistor, pta6?pta1, irq r pu 70 ? 120 k ? 2.0-volt dc electrical characteristics mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 151 13.7 2.0-volt dc el ectrical characteristics characteristic (1) 1. parameters are design targets at v dd = 2.0 10%, v ss = 0 vdc, t a = ?40c to +85c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?1.2 ma) (i load = ?2.0 ma) v oh v dd ?0.3 v dd ?1.0 ? ? ? ? v output low voltage (i load = 1.2 ma) (i load = 3.0 ma) (i load = 3.0 ma) pta7?pta0 only v ol ? ? ? ? ? ? 0.3 1.0 0.3 v input high voltage, all ports, irq , osc1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage, all ports, irq , osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) (f op = 2.0 mhz) wait (4) (f op = 2.0 mhz) stop (5) 25 c ?40 c to 85 c 25 c with lvi enabled ?40 c to 85 c with lvi enabled 3. run (operating) i dd measured using internal clock generator module (f op = 2.0 mhz). v dd = 2.0 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on a ll outputs. all ports configured as inputs. c l = 20 pf. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using internal clock generator module, f op = 2.0 mhz. all inputs 0.2 v fr om rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf. osc2 capacitance linearly affects wait i dd . all ports configured as inputs. 5. stop i dd measured with no port pins sourcing current, all modules disabled except as noted. i dd ? ? ? ? ? ? ? ? 10 ? 50 ? 2.5 850 ? 100 ? 350 ma ma na na a a i/o ports high-impedance leakage current (6) 6. pullups and pulldowns are disabled. i il ?? 1 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) 7. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (8) 8. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate (9) 9. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ?8v pullup resistor, pta6?pta1, irq r pu 70 ? 120 k ? electrical specifications mc68hc908rk2 data sheet, rev. 5.1 152 freescale semiconductor 13.8 control timing 13.9 internal osc illator characteristics characteristic (1) 1. v dd = 1.8 v to 3.3 v, v ss = 0 vdc, t a = ?40c to +85c, unless otherwise noted symbol min max unit bus operating frequency v dd = 3.0 v 10% v dd = 2.0 v 10% f bus 32 k 32 k 4.0 m 2.0 m hz reset pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 ? t cyc irq interrupt pulse period t ilil note 4 ? t cyc 16-bit timer (2) input capture pulse width (3) input capture period input clock pulse width 2. the 2-bit timer prescaler is the limitin g factor in determining timer resolution. 3. refer to table 11-3. mode, edge, and level selection and supporting note. t th, t tl t tltl t tch , t tcl 2 note (4) (1/f op ) + 5 4. the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 2 t cyc . ? ? ? t cyc t cyc ns characteristic (1) 1. v dd = 1.8 v to 3.3 v, v ss = 0 vdc, t a = ?40 o c to +85 o c, unless otherwise noted symbol min typ max unit internal oscillator base frequency without trim (2) (3) 2. internal oscillator is selectable through software for a maximum frequency,. actual frequency will be multiplier (n) x base frequency. 3. f bus = (f intosc / 4) x (internal oscillator multiplier) f intosc 230.4 307.2 384.0 khz internal oscillator base frequency with trim (2) (3) f intosc(i) 301.1 307.2 313.3 khz internal oscillator multiplier (4) 4. multiplier must be chosen to limit the maximum bus frequency to the maximum listed in 13.8 control timing . n1?127? external clock option (5) 3 v 10% 2 v 10% 5. no more than 10% duty cycle deviation from 50% f extosc 128 k 128 k ? ? 16 8 mhz lvi characteristics mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 153 13.10 lvi characteristics characteristics symbol min typ max unit lvi low battery sense voltage (1) 1. the lvi samples v dd , v lvr , and v lvs are v dd voltages. 2. v lv s 1.9 2.00 2.15 v lv i tr i p vo l t a g e (1) v lv r 1.76 1.85 2.00 v lvi trip voltage hysteresis h lv r 50 70 90 mv v dd slew rate ? rising sr r ? ? 0.05 v/ s v dd slew rate ? falling sr f ? ? 0.10 v/ s response time ? sr sr max t resp ??6.0 s response time ? sr > sr max t resp ?? note (2) s enable time (enable to output transition) t en ??50 s v dd v lvr ? sr max ----------------------------------- v dd v lvr ? sr ----------------------------------- ? ?? ?? ?? 1.5 + electrical specifications mc68hc908rk2 data sheet, rev. 5.1 154 freescale semiconductor 13.11 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash pages per row ? 8 ? 8 pages flash bytes per page ? 1 ? 1 bytes flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32 k ? 2.5 m hz flash charge pump clock frequency (see 2.5.2 flash 2ts charge pump frequency control ) f pump (2) 2. f pump is defined as the charge pump clock frequency r equired for program, erase, and margin read operations. 1.8 ? 2.5 mhz flash block/bulk erase time t erase 30 ? ? ms flash high voltage kill time t kill 200 ? ? ms flash return to read time t hvd 50 ? ? ms flash page program pulses fls pulses (3) 3. fls pulses is defined as the number of pulses used to program the flash using the requir ed smart program algorithm. ? ? 10 pulses flash page program step size t step (4) 4. t step is defined as the amount of time during one pag e program cycle that hven is held high. 1.0 ? 1.2 ms flash cumulative program time per row between erase cycles t row (5) 5. t row is defined as the cumulative time a row can see the pr ogram voltage before the row mu st be erased before further programming. ?? 8 page program cycles flash hven low to margin high time t hvtv 50 ? ? ms flash margin high to pgm low time t vtp 150 ? ? ms flash 2ts row program endurance (6) 6. the minimum row endurance value specif ies each row of the flash 2ts memory is guaranteed to work for at least this many erase/program cycles. ? 10 4 -? -? cycles flash data retention time (7) 7. the flash is guaranteed to retain data over the entire temperat ure range for at least the minimum time specified. ? 15 100 -? years mc68hc908rk2 data sheet, rev. 5.1 freescale semiconductor 155 chapter 14 order information and mechanical specifications 14.1 introduction this section contains ordering numbers for th e mc68hc908rk2. dimensions are given for: 20-pin shrink small outline package (ssop) package (case 940c-03) 20-pin small outline integrated circuit (soic) package (case 751d-05) 14.2 mc order numbers figure 14-1. device numbering system table 14-1. mc order numbers mc order number (1) 1. sd = ssop dw = soic operating temperature range mc68hc908rk2csd ?40 c to +85 c MC68HC908RK2DW ?40 c to +85 c m c 6 8 h c 9 0 8 r k 2 x x x family package designator temperature range order information and mechanical specifications mc68hc908rk2 data sheet, rev. 5.1 156 freescale semiconductor 14.3 20-pin plastic ssop package (case no. 940c-03) 14.4 20-pin soic plastic package (cas e no. 751d-05) 20 11 10 1 h a b f m k 20x ref s u m 0.12 (0.005) v s t l l/2 pin 1 ident s u m 0.20 (0.008) t ?v? ?u? d c 0.076 (0.003) g ?t? seating plane detail e n n 0.25 (0.010) ???? ???? k j j1 k1 section n?n dim a min max min max inches 7.07 7.33 0.278 0.288 millimeters b 5.20 5.38 0.205 0.212 c 1.73 1.99 0.068 0.078 d 0.05 0.21 0.002 0.008 f 0.63 0.95 0.024 0.037 g 0.65 bsc 0.026 bsc h 0.59 0.75 0.023 0.030 j 0.09 0.20 0.003 0.008 j1 0.09 0.16 0.003 0.006 k 0.25 0.38 0.010 0.015 k1 0.25 0.33 0.010 0.013 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 (0.006) per side. 5. dimension k does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of k dimension at maximum material condition. dambar intrusion shall not reduce dimension k by more than 0.07 (0.002) at least material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. l 7.65 7.90 0.301 0.311 m 0 8 0 8 detail e ?w? ! " # ! $ -a- -b- p 10 pl 110 11 20 -t- d 20 pl k c r x 45 m ! ! g 18 pl f j how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc908rk2 rev. 5.1, 08/2005 |
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